Commit dbf92186 authored by Martin Blumenstingl's avatar Martin Blumenstingl Committed by Neil Armstrong
Browse files

ARM: dts: amlogic: meson8b: switch to the new PWM controller binding 



Use the new PWM controller binding which now relies on passing all
clock inputs available on the SoC (instead of passing the "wanted"
clock input for a given board).

Signed-off-by: default avatarMartin Blumenstingl <martin.blumenstingl@googlemail.com>
Reviewed-by: default avatarNeil Armstrong <neil.armstrong@linaro.org>
Link: https://lore.kernel.org/r/20241227212514.1376682-3-martin.blumenstingl@googlemail.com


Signed-off-by: default avatarNeil Armstrong <neil.armstrong@linaro.org>
parent 802cff46

arch/arm/boot/dts/amlogic/meson8b-ec100.dts

+0 −2
Original line number Diff line number Diff line
@@ -443,8 +443,6 @@ &pwm_cd { 
	status = "okay";

	pinctrl-0 = <&pwm_c1_pins>, <&pwm_d_pins>;

	pinctrl-names = "default";

	clocks = <&xtal>, <&xtal>;

	clock-names = "clkin0", "clkin1";

};



&rtc {

arch/arm/boot/dts/amlogic/meson8b-mxq.dts

+0 −2
Original line number Diff line number Diff line
@@ -162,8 +162,6 @@ &pwm_cd { 
	status = "okay";

	pinctrl-0 = <&pwm_c1_pins>, <&pwm_d_pins>;

	pinctrl-names = "default";

	clocks = <&xtal>, <&xtal>;

	clock-names = "clkin0", "clkin1";

};



&uart_AO {

arch/arm/boot/dts/amlogic/meson8b-odroidc1.dts

+0 −2
Original line number Diff line number Diff line
@@ -347,8 +347,6 @@ &pwm_cd { 
	status = "okay";

	pinctrl-0 = <&pwm_c1_pins>, <&pwm_d_pins>;

	pinctrl-names = "default";

	clocks = <&xtal>, <&xtal>;

	clock-names = "clkin0", "clkin1";

};



&rtc {

arch/arm/boot/dts/amlogic/meson8b.dtsi

+15 −3
Original line number Diff line number Diff line
@@ -403,8 +403,12 @@ analog_top: analog-top@81a8 { 
	};



	pwm_ef: pwm@86c0 {

		compatible = "amlogic,meson8b-pwm";

		compatible = "amlogic,meson8b-pwm-v2", "amlogic,meson8-pwm-v2";

		reg = <0x86c0 0x10>;

		clocks = <&xtal>,

			 <>, /* unknown/untested, the datasheet calls it "Video PLL" */

			 <&clkc CLKID_FCLK_DIV4>,

			 <&clkc CLKID_FCLK_DIV3>;

		#pwm-cells = <3>;

		status = "disabled";

	};
@@ -674,11 +678,19 @@ timer@600 { 
};



&pwm_ab {

	compatible = "amlogic,meson8b-pwm";

	compatible = "amlogic,meson8b-pwm-v2", "amlogic,meson8-pwm-v2";

	clocks = <&xtal>,

		 <>, /* unknown/untested, the datasheet calls it "Video PLL" */

		 <&clkc CLKID_FCLK_DIV4>,

		 <&clkc CLKID_FCLK_DIV3>;

};



&pwm_cd {

	compatible = "amlogic,meson8b-pwm";

	compatible = "amlogic,meson8b-pwm-v2", "amlogic,meson8-pwm-v2";

	clocks = <&xtal>,

		 <>, /* unknown/untested, the datasheet calls it "Video PLL" */

		 <&clkc CLKID_FCLK_DIV4>,

		 <&clkc CLKID_FCLK_DIV3>;

};



&rtc {