Commit dbfd50cb authored by Paolo Bonzini's avatar Paolo Bonzini
Browse files

Merge tag 'kvm-x86-selftests-6.11' of https://github.com/kvm-x86/linux into HEAD 

KVM selftests for 6.11

 - Remove dead code in the memslot modification stress test.

 - Treat "branch instructions retired" as supported on all AMD Family 17h+ CPUs.

 - Print the guest pseudo-RNG seed only when it changes, to avoid spamming the
   log for tests that create lots of VMs.

 - Make the PMU counters test less flaky when counting LLC cache misses by
   doing CLFLUSH{OPT} in every loop iteration.
parents cda231cd 4669de42

tools/testing/selftests/kvm/lib/kvm_util.c

+7 −2
Original line number Diff line number Diff line
@@ -21,6 +21,7 @@ 


uint32_t guest_random_seed;

struct guest_random_state guest_rng;

static uint32_t last_guest_seed;



static int vcpu_mmap_sz(void);
@@ -434,7 +435,10 @@ struct kvm_vm *__vm_create(struct vm_shape shape, uint32_t nr_runnable_vcpus, 
	slot0 = memslot2region(vm, 0);

	ucall_init(vm, slot0->region.guest_phys_addr + slot0->region.memory_size);



	if (guest_random_seed != last_guest_seed) {

		pr_info("Random seed: 0x%x\n", guest_random_seed);

		last_guest_seed = guest_random_seed;

	}

	guest_rng = new_guest_random_state(guest_random_seed);

	sync_global_to_guest(vm, guest_rng);
@@ -2319,7 +2323,8 @@ void __attribute((constructor)) kvm_selftest_init(void) 
	/* Tell stdout not to buffer its content. */

	setbuf(stdout, NULL);



	guest_random_seed = random();

	guest_random_seed = last_guest_seed = random();

	pr_info("Random seed: 0x%x\n", guest_random_seed);



	kvm_selftest_arch_init();

}

tools/testing/selftests/kvm/memslot_modification_stress_test.c

+0 −6
Original line number Diff line number Diff line
@@ -53,12 +53,6 @@ static void vcpu_worker(struct memstress_vcpu_args *vcpu_args) 
	}

}



struct memslot_antagonist_args {

	struct kvm_vm *vm;

	useconds_t delay;

	uint64_t nr_modifications;

};



static void add_remove_memslot(struct kvm_vm *vm, useconds_t delay,

			       uint64_t nr_modifications)

{

tools/testing/selftests/kvm/x86_64/pmu_counters_test.c

+29 −15
Original line number Diff line number Diff line
@@ -7,15 +7,28 @@ 
#include "pmu.h"

#include "processor.h"



/* Number of LOOP instructions for the guest measurement payload. */

#define NUM_BRANCHES		10

/* Number of iterations of the loop for the guest measurement payload. */

#define NUM_LOOPS			10



/* Each iteration of the loop retires one branch instruction. */

#define NUM_BRANCH_INSNS_RETIRED	(NUM_LOOPS)



/*

 * Number of instructions in each loop. 1 CLFLUSH/CLFLUSHOPT/NOP, 1 MFENCE,

 * 1 LOOP.

 */

#define NUM_INSNS_PER_LOOP		3



/*

 * Number of "extra" instructions that will be counted, i.e. the number of

 * instructions that are needed to set up the loop and then disabled the

 * counter.  1 CLFLUSH/CLFLUSHOPT/NOP, 1 MFENCE, 2 MOV, 2 XOR, 1 WRMSR.

 * instructions that are needed to set up the loop and then disable the

 * counter.  2 MOV, 2 XOR, 1 WRMSR.

 */

#define NUM_EXTRA_INSNS		7

#define NUM_INSNS_RETIRED	(NUM_BRANCHES + NUM_EXTRA_INSNS)

#define NUM_EXTRA_INSNS			5



/* Total number of instructions retired within the measured section. */

#define NUM_INSNS_RETIRED		(NUM_LOOPS * NUM_INSNS_PER_LOOP + NUM_EXTRA_INSNS)





static uint8_t kvm_pmu_version;

static bool kvm_has_perf_caps;
@@ -100,7 +113,7 @@ static void guest_assert_event_count(uint8_t idx, 
		GUEST_ASSERT_EQ(count, NUM_INSNS_RETIRED);

		break;

	case INTEL_ARCH_BRANCHES_RETIRED_INDEX:

		GUEST_ASSERT_EQ(count, NUM_BRANCHES);

		GUEST_ASSERT_EQ(count, NUM_BRANCH_INSNS_RETIRED);

		break;

	case INTEL_ARCH_LLC_REFERENCES_INDEX:

	case INTEL_ARCH_LLC_MISSES_INDEX:
@@ -120,7 +133,7 @@ static void guest_assert_event_count(uint8_t idx, 
	}



sanity_checks:

	__asm__ __volatile__("loop ." : "+c"((int){NUM_BRANCHES}));

	__asm__ __volatile__("loop ." : "+c"((int){NUM_LOOPS}));

	GUEST_ASSERT_EQ(_rdpmc(pmc), count);



	wrmsr(pmc_msr, 0xdead);
@@ -134,8 +147,8 @@ static void guest_assert_event_count(uint8_t idx, 
 * before the end of the sequence.

 *

 * If CLFUSH{,OPT} is supported, flush the cacheline containing (at least) the

 * start of the loop to force LLC references and misses, i.e. to allow testing

 * that those events actually count.

 * CLFUSH{,OPT} instruction on each loop iteration to force LLC references and

 * misses, i.e. to allow testing that those events actually count.

 *

 * If forced emulation is enabled (and specified), force emulation on a subset

 * of the measured code to verify that KVM correctly emulates instructions and
@@ -145,10 +158,11 @@ static void guest_assert_event_count(uint8_t idx, 
#define GUEST_MEASURE_EVENT(_msr, _value, clflush, FEP)				\

do {										\

	__asm__ __volatile__("wrmsr\n\t"					\

			     " mov $" __stringify(NUM_LOOPS) ", %%ecx\n\t"	\

			     "1:\n\t"						\

			     clflush "\n\t"					\

			     "mfence\n\t"					\

			     "1: mov $" __stringify(NUM_BRANCHES) ", %%ecx\n\t"	\

			     FEP "loop .\n\t"					\

			     FEP "loop 1b\n\t"					\

			     FEP "mov %%edi, %%ecx\n\t"				\

			     FEP "xor %%eax, %%eax\n\t"				\

			     FEP "xor %%edx, %%edx\n\t"				\
@@ -163,9 +177,9 @@ do { \ 
	wrmsr(pmc_msr, 0);							\

										\

	if (this_cpu_has(X86_FEATURE_CLFLUSHOPT))				\

		GUEST_MEASURE_EVENT(_ctrl_msr, _value, "clflushopt 1f", FEP);	\

		GUEST_MEASURE_EVENT(_ctrl_msr, _value, "clflushopt .", FEP);	\

	else if (this_cpu_has(X86_FEATURE_CLFLUSH))				\

		GUEST_MEASURE_EVENT(_ctrl_msr, _value, "clflush 1f", FEP);	\

		GUEST_MEASURE_EVENT(_ctrl_msr, _value, "clflush .", FEP);	\

	else									\

		GUEST_MEASURE_EVENT(_ctrl_msr, _value, "nop", FEP);		\

										\
@@ -500,7 +514,7 @@ static void guest_test_fixed_counters(void) 
		wrmsr(MSR_CORE_PERF_FIXED_CTR0 + i, 0);

		wrmsr(MSR_CORE_PERF_FIXED_CTR_CTRL, FIXED_PMC_CTRL(i, FIXED_PMC_KERNEL));

		wrmsr(MSR_CORE_PERF_GLOBAL_CTRL, FIXED_PMC_GLOBAL_CTRL_ENABLE(i));

		__asm__ __volatile__("loop ." : "+c"((int){NUM_BRANCHES}));

		__asm__ __volatile__("loop ." : "+c"((int){NUM_LOOPS}));

		wrmsr(MSR_CORE_PERF_GLOBAL_CTRL, 0);

		val = rdmsr(MSR_CORE_PERF_FIXED_CTR0 + i);

tools/testing/selftests/kvm/x86_64/pmu_event_filter_test.c

+5 −30
Original line number Diff line number Diff line
@@ -32,8 +32,8 @@ struct __kvm_pmu_event_filter { 


/*

 * This event list comprises Intel's known architectural events, plus AMD's

 * "retired branch instructions" for Zen1-Zen3 (and* possibly other AMD CPUs).

 * Note, AMD and Intel use the same encoding for instructions retired.

 * Branch Instructions Retired for Zen CPUs.  Note, AMD and Intel use the

 * same encoding for Instructions Retired.

 */

kvm_static_assert(INTEL_ARCH_INSTRUCTIONS_RETIRED == AMD_ZEN_INSTRUCTIONS_RETIRED);
@@ -353,38 +353,13 @@ static bool use_intel_pmu(void) 
	       kvm_pmu_has(X86_PMU_FEATURE_BRANCH_INSNS_RETIRED);

}



static bool is_zen1(uint32_t family, uint32_t model)

{

	return family == 0x17 && model <= 0x0f;

}



static bool is_zen2(uint32_t family, uint32_t model)

{

	return family == 0x17 && model >= 0x30 && model <= 0x3f;

}



static bool is_zen3(uint32_t family, uint32_t model)

{

	return family == 0x19 && model <= 0x0f;

}



/*

 * Determining AMD support for a PMU event requires consulting the AMD

 * PPR for the CPU or reference material derived therefrom. The AMD

 * test code herein has been verified to work on Zen1, Zen2, and Zen3.

 *

 * Feel free to add more AMD CPUs that are documented to support event

 * select 0xc2 umask 0 as "retired branch instructions."

 * On AMD, all Family 17h+ CPUs (Zen and its successors) use event encoding

 * 0xc2,0 for Branch Instructions Retired.

 */

static bool use_amd_pmu(void)

{

	uint32_t family = kvm_cpu_family();

	uint32_t model = kvm_cpu_model();



	return host_cpu_is_amd &&

		(is_zen1(family, model) ||

		 is_zen2(family, model) ||

		 is_zen3(family, model));

	return host_cpu_is_amd && kvm_cpu_family() >= 0x17;

}



/*