Commit dc30c6e7 authored by Ashutosh Dixit's avatar Ashutosh Dixit
Browse files

drm/xe: Label RING_CONTEXT_CONTROL as masked 



RING_CONTEXT_CONTROL is a masked register.

v2: Also clean up setting register value (Lucas)

Reviewed-by: default avatarMatt Roper <matthew.d.roper@intel.com>
Reviewed-by: default avatarLucas De Marchi <lucas.demarchi@intel.com>
Signed-off-by: default avatarAshutosh Dixit <ashutosh.dixit@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20240404161256.3852502-1-ashutosh.dixit@intel.com
parent 335ad807

drivers/gpu/drm/xe/regs/xe_engine_regs.h

+1 −1
Original line number Diff line number Diff line
@@ -122,7 +122,7 @@ 
#define RING_EXECLIST_STATUS_LO(base)		XE_REG((base) + 0x234)

#define RING_EXECLIST_STATUS_HI(base)		XE_REG((base) + 0x234 + 4)



#define RING_CONTEXT_CONTROL(base)		XE_REG((base) + 0x244)

#define RING_CONTEXT_CONTROL(base)		XE_REG((base) + 0x244, XE_REG_OPTION_MASKED)

#define	  CTX_CTRL_INHIBIT_SYN_CTX_SWITCH	REG_BIT(3)

#define	  CTX_CTRL_ENGINE_CTX_RESTORE_INHIBIT	REG_BIT(0)

drivers/gpu/drm/xe/xe_lrc.c

+2 −3
Original line number Diff line number Diff line
@@ -543,9 +543,8 @@ static const u8 *reg_offsets(struct xe_device *xe, enum xe_engine_class class) 


static void set_context_control(u32 *regs, struct xe_hw_engine *hwe)

{

	regs[CTX_CONTEXT_CONTROL] = _MASKED_BIT_ENABLE(CTX_CTRL_INHIBIT_SYN_CTX_SWITCH) |

				    _MASKED_BIT_DISABLE(CTX_CTRL_ENGINE_CTX_RESTORE_INHIBIT) |

				    CTX_CTRL_ENGINE_CTX_RESTORE_INHIBIT;

	regs[CTX_CONTEXT_CONTROL] = _MASKED_BIT_ENABLE(CTX_CTRL_INHIBIT_SYN_CTX_SWITCH |

						       CTX_CTRL_ENGINE_CTX_RESTORE_INHIBIT);



	/* TODO: Timestamp */

}