Commit dc6d5d85 authored by Sameer Pujar's avatar Sameer Pujar Committed by Thierry Reding
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arm64: tegra: Update AHUB clock parent and rate 



I2S data sanity test failures are seen at lower AHUB clock rates
on Tegra234. The Tegra194 uses the same clock relationship for AHUB
and it is likely that similar issues would be seen. Thus update the
AHUB clock parent and rates here as well for Tegra194, Tegra186
and Tegra210.

Fixes: 177208f7 ("arm64: tegra: Add DT binding for AHUB components")
Cc: stable@vger.kernel.org
Signed-off-by: default avatarSameer Pujar <spujar@nvidia.com>
Signed-off-by: default avatarThierry Reding <treding@nvidia.com>
parent e483fe34

arch/arm64/boot/dts/nvidia/tegra186.dtsi

+2 −1
Original line number Diff line number Diff line
@@ -135,7 +135,8 @@ tegra_ahub: ahub@2900800 { 
			clocks = <&bpmp TEGRA186_CLK_AHUB>;

			clock-names = "ahub";

			assigned-clocks = <&bpmp TEGRA186_CLK_AHUB>;

			assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>;

			assigned-clock-parents = <&bpmp TEGRA186_CLK_PLLP_OUT0>;

			assigned-clock-rates = <81600000>;

			#address-cells = <1>;

			#size-cells = <1>;

			ranges = <0x02900800 0x02900800 0x11800>;

arch/arm64/boot/dts/nvidia/tegra194.dtsi

+2 −1
Original line number Diff line number Diff line
@@ -231,7 +231,8 @@ tegra_ahub: ahub@2900800 { 
				clocks = <&bpmp TEGRA194_CLK_AHUB>;

				clock-names = "ahub";

				assigned-clocks = <&bpmp TEGRA194_CLK_AHUB>;

				assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>;

				assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLP_OUT0>;

				assigned-clock-rates = <81600000>;

				status = "disabled";



				#address-cells = <2>;

arch/arm64/boot/dts/nvidia/tegra210.dtsi

+2 −1
Original line number Diff line number Diff line
@@ -1386,7 +1386,8 @@ tegra_ahub: ahub@702d0800 { 
			clocks = <&tegra_car TEGRA210_CLK_D_AUDIO>;

			clock-names = "ahub";

			assigned-clocks = <&tegra_car TEGRA210_CLK_D_AUDIO>;

			assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_A_OUT0>;

			assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_P>;

			assigned-clock-rates = <81600000>;

			#address-cells = <1>;

			#size-cells = <1>;

			ranges = <0x702d0000 0x702d0000 0x0000e400>;