Commit dc71d92f authored by Ovidiu Panait's avatar Ovidiu Panait Committed by Geert Uytterhoeven
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clk: renesas: r9a09g056: Fix ordering of module clocks array 



The r9a09g056_mod_clks array is sorted by CPG_CLKON register number and
bit position.  Move the RSPI 0/1/2 module clock entries to their correct
position to restore the array sort order.

Fixes: 1f76689d ("clk: renesas: r9a09g056: Add entries for RSCIs")
Signed-off-by: default avatarOvidiu Panait <ovidiu.panait.rb@renesas.com>
Reviewed-by: default avatarGeert Uytterhoeven <geert+renesas@glider.be>
Link: https://patch.msgid.link/20260125192706.27099-2-ovidiu.panait.rb@renesas.com


Signed-off-by: default avatarGeert Uytterhoeven <geert+renesas@glider.be>
parent 79cac2b8

drivers/clk/renesas/r9a09g056-cpg.c

+18 −18
Original line number Diff line number Diff line
@@ -289,6 +289,24 @@ static const struct rzv2h_mod_clk r9a09g056_mod_clks[] __initconst = { 
						BUS_MSTOP(5, BIT(13))),

	DEF_MOD("wdt_3_clk_loco",		CLK_QEXTAL, 5, 2, 2, 18,

						BUS_MSTOP(5, BIT(13))),

	DEF_MOD("rspi_0_pclk",			CLK_PLLCLN_DIV8, 5, 4, 2, 20,

						BUS_MSTOP(11, BIT(0))),

	DEF_MOD("rspi_0_pclk_sfr",		CLK_PLLCLN_DIV8, 5, 5, 2, 21,

						BUS_MSTOP(11, BIT(0))),

	DEF_MOD("rspi_0_tclk",			CLK_PLLCLN_DIV8, 5, 6, 2, 22,

						BUS_MSTOP(11, BIT(0))),

	DEF_MOD("rspi_1_pclk",			CLK_PLLCLN_DIV8, 5, 7, 2, 23,

						BUS_MSTOP(11, BIT(1))),

	DEF_MOD("rspi_1_pclk_sfr",		CLK_PLLCLN_DIV8, 5, 8, 2, 24,

						BUS_MSTOP(11, BIT(1))),

	DEF_MOD("rspi_1_tclk",			CLK_PLLCLN_DIV8, 5, 9, 2, 25,

						BUS_MSTOP(11, BIT(1))),

	DEF_MOD("rspi_2_pclk",			CLK_PLLCLN_DIV8, 5, 10, 2, 26,

						BUS_MSTOP(11, BIT(2))),

	DEF_MOD("rspi_2_pclk_sfr",		CLK_PLLCLN_DIV8, 5, 11, 2, 27,

						BUS_MSTOP(11, BIT(2))),

	DEF_MOD("rspi_2_tclk",			CLK_PLLCLN_DIV8, 5, 12, 2, 28,

						BUS_MSTOP(11, BIT(2))),

	DEF_MOD("rsci0_pclk",			CLK_PLLCLN_DIV16, 5, 13, 2, 29,

						BUS_MSTOP(11, BIT(3))),

	DEF_MOD("rsci0_tclk",			CLK_PLLCLN_DIV16, 5, 14, 2, 30,
@@ -389,24 +407,6 @@ static const struct rzv2h_mod_clk r9a09g056_mod_clks[] __initconst = { 
						BUS_MSTOP(11, BIT(12))),

	DEF_MOD("rsci9_ps_ps1_n",		CLK_PLLCLN_DIV64, 8, 14, 4, 14,

						BUS_MSTOP(11, BIT(12))),

	DEF_MOD("rspi_0_pclk",			CLK_PLLCLN_DIV8, 5, 4, 2, 20,

						BUS_MSTOP(11, BIT(0))),

	DEF_MOD("rspi_0_pclk_sfr",		CLK_PLLCLN_DIV8, 5, 5, 2, 21,

						BUS_MSTOP(11, BIT(0))),

	DEF_MOD("rspi_0_tclk",			CLK_PLLCLN_DIV8, 5, 6, 2, 22,

						BUS_MSTOP(11, BIT(0))),

	DEF_MOD("rspi_1_pclk",			CLK_PLLCLN_DIV8, 5, 7, 2, 23,

						BUS_MSTOP(11, BIT(1))),

	DEF_MOD("rspi_1_pclk_sfr",		CLK_PLLCLN_DIV8, 5, 8, 2, 24,

						BUS_MSTOP(11, BIT(1))),

	DEF_MOD("rspi_1_tclk",			CLK_PLLCLN_DIV8, 5, 9, 2, 25,

						BUS_MSTOP(11, BIT(1))),

	DEF_MOD("rspi_2_pclk",			CLK_PLLCLN_DIV8, 5, 10, 2, 26,

						BUS_MSTOP(11, BIT(2))),

	DEF_MOD("rspi_2_pclk_sfr",		CLK_PLLCLN_DIV8, 5, 11, 2, 27,

						BUS_MSTOP(11, BIT(2))),

	DEF_MOD("rspi_2_tclk",			CLK_PLLCLN_DIV8, 5, 12, 2, 28,

						BUS_MSTOP(11, BIT(2))),

	DEF_MOD("scif_0_clk_pck",		CLK_PLLCM33_DIV16, 8, 15, 4, 15,

						BUS_MSTOP(3, BIT(14))),

	DEF_MOD("i3c_0_pclkrw",			CLK_PLLCLN_DIV16, 9, 0, 4, 16,