Commit dc84f52e authored by Yifan Zhang's avatar Yifan Zhang Committed by Alex Deucher
Browse files

drm/amdgpu/nbio: Add NBIO 7.11.1 Support



Fix up doorbell setup and clockgating.

v2: squash in fixes (Alex)

Signed-off-by: default avatarYifan Zhang <yifan1.zhang@amd.com>
Signed-off-by: default avatarLang Yu <Lang.Yu@amd.com>
Signed-off-by: default avatarVeerabadhran Gopalakrishnan <veerabadhran.gopalakrishnan@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 34a1de0f
Loading
Loading
Loading
Loading
+7 −2
Original line number Diff line number Diff line
@@ -89,7 +89,9 @@ static void nbio_v7_11_vpe_doorbell_range(struct amdgpu_device *adev, int instan
					  bool use_doorbell, int doorbell_index,
					  int doorbell_size)
{
	u32 reg = SOC15_REG_OFFSET(NBIO, 0, regGDC0_BIF_VPE_DOORBELL_RANGE);
	u32 reg = instance == 0 ?
		  SOC15_REG_OFFSET(NBIO, 0, regGDC0_BIF_VPE_DOORBELL_RANGE) :
		  SOC15_REG_OFFSET(NBIO, 0, regGDC0_BIF_VPE1_DOORBELL_RANGE);
	u32 doorbell_range = RREG32_PCIE_PORT(reg);

	if (use_doorbell) {
@@ -112,7 +114,10 @@ static void nbio_v7_11_vcn_doorbell_range(struct amdgpu_device *adev,
					  bool use_doorbell,
					  int doorbell_index, int instance)
{
	u32 reg = SOC15_REG_OFFSET(NBIO, 0, regGDC0_BIF_VCN0_DOORBELL_RANGE);
	u32 reg = instance == 0 ?
		SOC15_REG_OFFSET(NBIO, 0, regGDC0_BIF_VCN0_DOORBELL_RANGE):
		SOC15_REG_OFFSET(NBIO, 0, regGDC0_BIF_VCN1_DOORBELL_RANGE);

	u32 doorbell_range = RREG32_PCIE_PORT(reg);

	if (use_doorbell) {
+1 −0
Original line number Diff line number Diff line
@@ -866,6 +866,7 @@ static int soc21_common_set_clockgating_state(void *handle,
	case IP_VERSION(7, 7, 0):
	case IP_VERSION(7, 7, 1):
	case IP_VERSION(7, 11, 0):
	case IP_VERSION(7, 11, 1):
		adev->nbio.funcs->update_medium_grain_clock_gating(adev,
				state == AMD_CG_STATE_GATE);
		adev->nbio.funcs->update_medium_grain_light_sleep(adev,
+2 −0
Original line number Diff line number Diff line
@@ -8900,6 +8900,8 @@
#define regGDC0_BIF_IH_DOORBELL_RANGE_BASE_IDX                                                          3
#define regGDC0_BIF_VCN0_DOORBELL_RANGE                                                                 0x4f0af3
#define regGDC0_BIF_VCN0_DOORBELL_RANGE_BASE_IDX                                                        3
#define regGDC0_BIF_VPE1_DOORBELL_RANGE                                                                 0x4f0af4
#define regGDC0_BIF_VPE1_DOORBELL_RANGE_BASE_IDX                                                        3
#define regGDC0_BIF_RLC_DOORBELL_RANGE                                                                  0x4f0af5
#define regGDC0_BIF_RLC_DOORBELL_RANGE_BASE_IDX                                                         3
#define regGDC0_BIF_SDMA2_DOORBELL_RANGE                                                                0x4f0af6