Commit dc9b0c2a authored by Wenjing Liu's avatar Wenjing Liu Committed by Alex Deucher
Browse files

drm/amd/display: fix a pipe mapping error in dcn32_fpu 



[why]
In dcn32 DML pipes are ordered the same as dc pipes but only for used
pipes. For example, if dc pipe 1 and 2 are used, their dml pipe indices
would be 0 and 1 respectively. However
update_pipe_slice_table_with_split_flags doesn't skip indices for free
pipes. This causes us to not reference correct dml pipe output when
building pipe topology.

[how]
Use two variables to iterate dc and dml pipes respectively and only
increment dml pipe index when current dc pipe is not free.

Cc: stable@vger.kernel.org # 6.1+
Reviewed-by: default avatarChaitanya Dhere <chaitanya.dhere@amd.com>
Acked-by: default avatarHamza Mahfooz <hamza.mahfooz@amd.com>
Signed-off-by: default avatarWenjing Liu <wenjing.liu@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent fdf84f10

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

+12 −8
Original line number Diff line number Diff line
@@ -1192,13 +1192,16 @@ static bool update_pipe_slice_table_with_split_flags( 
	 */

	struct pipe_ctx *pipe;

	bool odm;

	int i;

	int dc_pipe_idx, dml_pipe_idx = 0;

	bool updated = false;



	for (i = 0; i < dc->res_pool->pipe_count; i++) {

		pipe = &context->res_ctx.pipe_ctx[i];

	for (dc_pipe_idx = 0;

			dc_pipe_idx < dc->res_pool->pipe_count; dc_pipe_idx++) {

		pipe = &context->res_ctx.pipe_ctx[dc_pipe_idx];

		if (resource_is_pipe_type(pipe, FREE_PIPE))

			continue;



		if (merge[i]) {

		if (merge[dc_pipe_idx]) {

			if (resource_is_pipe_type(pipe, OPP_HEAD))

				/* merging OPP head means reducing ODM slice

				 * count by 1
@@ -1213,17 +1216,18 @@ static bool update_pipe_slice_table_with_split_flags( 
			updated = true;

		}



		if (split[i]) {

			odm = vba->ODMCombineEnabled[vba->pipe_plane[i]] !=

		if (split[dc_pipe_idx]) {

			odm = vba->ODMCombineEnabled[vba->pipe_plane[dml_pipe_idx]] !=

					dm_odm_combine_mode_disabled;

			if (odm && resource_is_pipe_type(pipe, OPP_HEAD))

				update_slice_table_for_stream(

						table, pipe->stream, split[i] - 1);

						table, pipe->stream, split[dc_pipe_idx] - 1);

			else if (!odm && resource_is_pipe_type(pipe, DPP_PIPE))

				update_slice_table_for_plane(table, pipe,

						pipe->plane_state, split[i] - 1);

						pipe->plane_state, split[dc_pipe_idx] - 1);

			updated = true;

		}

		dml_pipe_idx++;

	}

	return updated;

}