Commit dceb3667 authored by Arnd Bergmann's avatar Arnd Bergmann
Browse files

Merge branch 'newsoc/axiado' into soc/newsoc 

Support for the AX3000 SoC, from Harshit Shah <hshah@axiado.com>:

The AX3000 is a multi-core system-on-chip featuring four ARM Cortex-A53
cores, secure vault, hardware firewall, and AI acceleration engines. This
initial support enables basic bring-up of the SoC and evaluation platform
with CPU, timer, UART, and I3C functionality.

The series begins by adding the "axiado" vendor prefix and compatible
strings for the SoC and board. It then introduces the device tree files
and minimal ARCH_AXIADO platform support in arm64.

* newsoc/axiado:
  MAINTAINERS: Add entry for Axiado
  arm64: defconfig: enable the Axiado family
  arm64: dts: axiado: Add initial support for AX3000 SoC and eval board
  arm64: add Axiado SoC family
  dt-bindings: i3c: cdns: add Axiado AX3000 I3C controller
  dt-bindings: serial: cdns: add Axiado AX3000 UART controller
  dt-bindings: gpio: cdns: add Axiado AX3000 GPIO variant
  dt-bindings: gpio: cdns: convert to YAML
  dt-bindings: arm: axiado: add AX3000 EVK compatible strings
  dt-bindings: vendor-prefixes: Add Axiado Corporation
parents c5b9bff3 a6beb2bd

Documentation/devicetree/bindings/arm/axiado.yaml

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# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause

%YAML 1.2

---

$id: http://devicetree.org/schemas/arm/axiado.yaml#

$schema: http://devicetree.org/meta-schemas/core.yaml#



title: Axiado Platforms



maintainers:

  - Harshit Shah <hshah@axiado.com>



properties:

  $nodename:

    const: '/'

  compatible:

    oneOf:

      - description: AX3000 based boards

        items:

          - enum:

              - axiado,ax3000-evk       # Axiado AX3000 Evaluation Board

          - const: axiado,ax3000       # Axiado AX3000 SoC



additionalProperties: true

Documentation/devicetree/bindings/gpio/cdns,gpio.txt

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Cadence GPIO controller bindings



Required properties:

- compatible: should be "cdns,gpio-r1p02".

- reg: the register base address and size.

- #gpio-cells: should be 2.

	* first cell is the GPIO number.

	* second cell specifies the GPIO flags, as defined in

		<dt-bindings/gpio/gpio.h>. Only the GPIO_ACTIVE_HIGH

		and GPIO_ACTIVE_LOW flags are supported.

- gpio-controller: marks the device as a GPIO controller.

- clocks: should contain one entry referencing the peripheral clock driving

	the GPIO controller.



Optional properties:

- ngpios: integer number of gpio lines supported by this controller, up to 32.

- interrupts: interrupt specifier for the controllers interrupt.

- interrupt-controller: marks the device as an interrupt controller. When

	defined, interrupts, interrupt-parent and #interrupt-cells

	are required.

- interrupt-cells: should be 2.

	* first cell is the GPIO number you want to use as an IRQ source.

	* second cell specifies the IRQ type, as defined in

		<dt-bindings/interrupt-controller/irq.h>.

		Currently only level sensitive IRQs are supported.





Example:

	gpio0: gpio-controller@fd060000 {

		compatible = "cdns,gpio-r1p02";

		reg =<0xfd060000 0x1000>;



		clocks = <&gpio_clk>;



		interrupt-parent = <&gic>;

		interrupts = <0 5 IRQ_TYPE_LEVEL_HIGH>;



		gpio-controller;

		#gpio-cells = <2>;



		interrupt-controller;

		#interrupt-cells = <2>;

	};

Documentation/devicetree/bindings/gpio/cdns,gpio.yaml

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# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)

%YAML 1.2

---

$id: http://devicetree.org/schemas/gpio/cdns,gpio.yaml#

$schema: http://devicetree.org/meta-schemas/core.yaml#



title: Cadence GPIO Controller



maintainers:

  - Jan Kotas <jank@cadence.com>



properties:

  compatible:

    oneOf:

      - const: cdns,gpio-r1p02

      - items:

          - enum:

              - axiado,ax3000-gpio

          - const: cdns,gpio-r1p02



  reg:

    maxItems: 1



  clocks:

    maxItems: 1



  ngpios:

    minimum: 1

    maximum: 32



  gpio-controller: true



  "#gpio-cells":

    const: 2

    description: |

      - First cell is the GPIO line number.

      - Second cell is flags as defined in <dt-bindings/gpio/gpio.h>,

        only GPIO_ACTIVE_HIGH and GPIO_ACTIVE_LOW supported.



  interrupt-controller: true



  "#interrupt-cells":

    const: 2

    description: |

      - First cell is the GPIO line number used as IRQ.

      - Second cell is the trigger type, as defined in

        <dt-bindings/interrupt-controller/irq.h>.



  interrupts:

    maxItems: 1



required:

  - compatible

  - reg

  - clocks

  - gpio-controller

  - "#gpio-cells"



if:

  required: [interrupt-controller]

then:

  required:

    - interrupts



additionalProperties: false



examples:

  - |

    #include <dt-bindings/interrupt-controller/arm-gic.h>

    #include <dt-bindings/interrupt-controller/irq.h>

    gpio0: gpio-controller@fd060000 {

        compatible = "cdns,gpio-r1p02";

        reg = <0xfd060000 0x1000>;

        clocks = <&gpio_clk>;



        interrupt-parent = <&gic>;

        interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;



        gpio-controller;

        #gpio-cells = <2>;



        interrupt-controller;

        #interrupt-cells = <2>;

    };

Documentation/devicetree/bindings/i3c/cdns,i3c-master.yaml

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@@ -14,7 +14,12 @@ allOf: 


properties:

  compatible:

    const: cdns,i3c-master

    oneOf:

      - const: cdns,i3c-master

      - items:

          - enum:

              - axiado,ax3000-i3c

          - const: cdns,i3c-master



  reg:

    maxItems: 1

Documentation/devicetree/bindings/serial/cdns,uart.yaml

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@@ -16,9 +16,10 @@ properties: 
        items:

          - const: xlnx,xuartps

          - const: cdns,uart-r1p8

      - description: UART controller for Zynq Ultrascale+ MPSoC

        items:

          - const: xlnx,zynqmp-uart

      - items:

          - enum:

              - axiado,ax3000-uart

              - xlnx,zynqmp-uart

          - const: cdns,uart-r1p12



  reg: