Commit dd01714e authored by Dave Airlie's avatar Dave Airlie
Browse files

Merge tag 'drm-intel-fixes-2023-10-05' of... 

Merge tag 'drm-intel-fixes-2023-10-05' of git://anongit.freedesktop.org/drm/drm-intel

 into drm-fixes

- Fix for OpenGL CTS regression on Compute Shaders (Nirmoy)
- Fix for default engines initialization (Mathias)
- Fix TLB invalidation for Multi-GT devices (Chris)

Signed-off-by: default avatarDave Airlie <airlied@redhat.com>

From: Rodrigo Vivi <rodrigo.vivi@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/ZR7EvL+ucWI4uDTX@intel.com
parents 8a749fd1 1fbb6c1d

drivers/gpu/drm/i915/gem/i915_gem_pages.c

+1 −1
Original line number Diff line number Diff line
@@ -198,7 +198,7 @@ static void flush_tlb_invalidate(struct drm_i915_gem_object *obj) 


	for_each_gt(gt, i915, id) {

		if (!obj->mm.tlb[id])

			return;

			continue;



		intel_gt_invalidate_tlb_full(gt, obj->mm.tlb[id]);

		obj->mm.tlb[id] = 0;

drivers/gpu/drm/i915/gt/gen8_engine_cs.c

+10 −1
Original line number Diff line number Diff line
@@ -271,8 +271,17 @@ int gen12_emit_flush_rcs(struct i915_request *rq, u32 mode) 
		if (GRAPHICS_VER_FULL(rq->i915) >= IP_VER(12, 70))

			bit_group_0 |= PIPE_CONTROL_CCS_FLUSH;



		bit_group_1 |= PIPE_CONTROL_TILE_CACHE_FLUSH;

		/*

		 * L3 fabric flush is needed for AUX CCS invalidation

		 * which happens as part of pipe-control so we can

		 * ignore PIPE_CONTROL_FLUSH_L3. Also PIPE_CONTROL_FLUSH_L3

		 * deals with Protected Memory which is not needed for

		 * AUX CCS invalidation and lead to unwanted side effects.

		 */

		if (mode & EMIT_FLUSH)

			bit_group_1 |= PIPE_CONTROL_FLUSH_L3;



		bit_group_1 |= PIPE_CONTROL_TILE_CACHE_FLUSH;

		bit_group_1 |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH;

		bit_group_1 |= PIPE_CONTROL_DEPTH_CACHE_FLUSH;

		/* Wa_1409600907:tgl,adl-p */

drivers/gpu/drm/i915/i915_gem.c

+7 −2
Original line number Diff line number Diff line
@@ -1199,6 +1199,13 @@ int i915_gem_init(struct drm_i915_private *dev_priv) 
			goto err_unlock;

	}



	/*

	 * Register engines early to ensure the engine list is in its final

	 * rb-tree form, lowering the amount of code that has to deal with

	 * the intermediate llist state.

	 */

	intel_engines_driver_register(dev_priv);



	return 0;



	/*
@@ -1246,8 +1253,6 @@ int i915_gem_init(struct drm_i915_private *dev_priv) 
void i915_gem_driver_register(struct drm_i915_private *i915)

{

	i915_gem_driver_register__shrinker(i915);



	intel_engines_driver_register(i915);

}



void i915_gem_driver_unregister(struct drm_i915_private *i915)