Commit dd036502 authored by Dave Airlie's avatar Dave Airlie
Browse files

Merge tag 'amd-drm-fixes-7.0-2026-03-12' of... 

Merge tag 'amd-drm-fixes-7.0-2026-03-12' of https://gitlab.freedesktop.org/agd5f/linux

 into drm-fixes

amd-drm-fixes-7.0-2026-03-12:

amdgpu:
- SMU13 fix
- SMU14 fix
- Fixes for bringup hw testing
- Kerneldoc fix
- GC12 idle power fix for compute workloads
- DCCG fixes

amdkfd:
- Fix missing BO unreserve in an error path

Signed-off-by: default avatarDave Airlie <airlied@redhat.com>

From: Alex Deucher <alexander.deucher@amd.com>
Link: https://patch.msgid.link/20260312180351.3874990-1-alexander.deucher@amd.com
parents 8c835a10 3646ff28

drivers/gpu/drm/amd/amdgpu/amdgpu_device.c

+13 −1
Original line number Diff line number Diff line
@@ -2690,8 +2690,10 @@ static int amdgpu_device_ip_early_init(struct amdgpu_device *adev) 
		break;

	default:

		r = amdgpu_discovery_set_ip_blocks(adev);

		if (r)

		if (r) {

			adev->num_ip_blocks = 0;

			return r;

		}

		break;

	}
@@ -3247,6 +3249,8 @@ int amdgpu_device_set_cg_state(struct amdgpu_device *adev, 
		i = state == AMD_CG_STATE_GATE ? j : adev->num_ip_blocks - j - 1;

		if (!adev->ip_blocks[i].status.late_initialized)

			continue;

		if (!adev->ip_blocks[i].version)

			continue;

		/* skip CG for GFX, SDMA on S0ix */

		if (adev->in_s0ix &&

		    (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_GFX ||
@@ -3286,6 +3290,8 @@ int amdgpu_device_set_pg_state(struct amdgpu_device *adev, 
		i = state == AMD_PG_STATE_GATE ? j : adev->num_ip_blocks - j - 1;

		if (!adev->ip_blocks[i].status.late_initialized)

			continue;

		if (!adev->ip_blocks[i].version)

			continue;

		/* skip PG for GFX, SDMA on S0ix */

		if (adev->in_s0ix &&

		    (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_GFX ||
@@ -3493,6 +3499,8 @@ static int amdgpu_device_ip_fini_early(struct amdgpu_device *adev) 
	int i, r;



	for (i = 0; i < adev->num_ip_blocks; i++) {

		if (!adev->ip_blocks[i].version)

			continue;

		if (!adev->ip_blocks[i].version->funcs->early_fini)

			continue;
@@ -3570,6 +3578,8 @@ static int amdgpu_device_ip_fini(struct amdgpu_device *adev) 
		if (!adev->ip_blocks[i].status.sw)

			continue;



		if (!adev->ip_blocks[i].version)

			continue;

		if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_GMC) {

			amdgpu_ucode_free_bo(adev);

			amdgpu_free_static_csa(&adev->virt.csa_obj);
@@ -3596,6 +3606,8 @@ static int amdgpu_device_ip_fini(struct amdgpu_device *adev) 
	for (i = adev->num_ip_blocks - 1; i >= 0; i--) {

		if (!adev->ip_blocks[i].status.late_initialized)

			continue;

		if (!adev->ip_blocks[i].version)

			continue;

		if (adev->ip_blocks[i].version->funcs->late_fini)

			adev->ip_blocks[i].version->funcs->late_fini(&adev->ip_blocks[i]);

		adev->ip_blocks[i].status.late_initialized = false;

drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c

+1 −1
Original line number Diff line number Diff line
@@ -83,7 +83,7 @@ void amdgpu_driver_unload_kms(struct drm_device *dev) 
{

	struct amdgpu_device *adev = drm_to_adev(dev);



	if (adev == NULL)

	if (adev == NULL || !adev->num_ip_blocks)

		return;



	amdgpu_unregister_gpu_instance(adev);

drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h

+8 −8
Original line number Diff line number Diff line
@@ -368,15 +368,15 @@ struct amdgpu_mode_info { 


	struct drm_property *plane_ctm_property;

	/**

	 * @shaper_lut_property: Plane property to set pre-blending shaper LUT

	 * that converts color content before 3D LUT. If

	 * plane_shaper_tf_property != Identity TF, AMD color module will

	 * @plane_shaper_lut_property: Plane property to set pre-blending

	 * shaper LUT that converts color content before 3D LUT.

	 * If plane_shaper_tf_property != Identity TF, AMD color module will

	 * combine the user LUT values with pre-defined TF into the LUT

	 * parameters to be programmed.

	 */

	struct drm_property *plane_shaper_lut_property;

	/**

	 * @shaper_lut_size_property: Plane property for the size of

	 * @plane_shaper_lut_size_property: Plane property for the size of

	 * pre-blending shaper LUT as supported by the driver (read-only).

	 */

	struct drm_property *plane_shaper_lut_size_property;
@@ -400,10 +400,10 @@ struct amdgpu_mode_info { 
	 */

	struct drm_property *plane_lut3d_property;

	/**

	 * @plane_degamma_lut_size_property: Plane property to define the max

	 * size of 3D LUT as supported by the driver (read-only). The max size

	 * is the max size of one dimension and, therefore, the max number of

	 * entries for 3D LUT array is the 3D LUT size cubed;

	 * @plane_lut3d_size_property: Plane property to define the max size

	 * of 3D LUT as supported by the driver (read-only). The max size is

	 * the max size of one dimension and, therefore, the max number of

	 * entries for 3D LUT array is the 3D LUT size cubed.

	 */

	struct drm_property *plane_lut3d_size_property;

	/**

drivers/gpu/drm/amd/amdgpu/mes_v12_0.c

+4 −1
Original line number Diff line number Diff line
@@ -731,6 +731,9 @@ static int mes_v12_0_set_hw_resources(struct amdgpu_mes *mes, int pipe) 
	int i;

	struct amdgpu_device *adev = mes->adev;

	union MESAPI_SET_HW_RESOURCES mes_set_hw_res_pkt;

	uint32_t mes_rev = (pipe == AMDGPU_MES_SCHED_PIPE) ?

		(mes->sched_version & AMDGPU_MES_VERSION_MASK) :

		(mes->kiq_version & AMDGPU_MES_VERSION_MASK);



	memset(&mes_set_hw_res_pkt, 0, sizeof(mes_set_hw_res_pkt));
@@ -785,7 +788,7 @@ static int mes_v12_0_set_hw_resources(struct amdgpu_mes *mes, int pipe) 
	 * handling support, other queue will not use the oversubscribe timer.

	 * handling  mode - 0: disabled; 1: basic version; 2: basic+ version

	 */

	mes_set_hw_res_pkt.oversubscription_timer = 50;

	mes_set_hw_res_pkt.oversubscription_timer = mes_rev < 0x8b ? 0 : 50;

	mes_set_hw_res_pkt.unmapped_doorbell_handling = 1;



	if (amdgpu_mes_log_enable) {

drivers/gpu/drm/amd/amdkfd/kfd_process_queue_manager.c

+1 −0
Original line number Diff line number Diff line
@@ -593,6 +593,7 @@ int pqm_update_queue_properties(struct process_queue_manager *pqm, 
					 p->queue_size)) {

			pr_debug("ring buf 0x%llx size 0x%llx not mapped on GPU\n",

				 p->queue_address, p->queue_size);

			amdgpu_bo_unreserve(vm->root.bo);

			return -EFAULT;

		}