Unverified Commit dd10ed1c authored by Mark Brown's avatar Mark Brown
Browse files

ASoC: convert from clk round_rate() to

Merge series from Brian Masney <bmasney@redhat.com>:

The round_rate() clk ops is deprecated in the clk framework in favor
of the determine_rate() clk ops, so let's go ahead and convert the
drivers in the rtc subsystem using the Coccinelle semantic patch
posted below. I did a few minor cosmetic cleanups of the code in a
few cases.

Coccinelle semantic patch:

    virtual patch

    // Look up the current name of the round_rate function
    @ has_round_rate @
    identifier round_rate_name =~ ".*_round_rate";
    identifier hw_param, rate_param, parent_rate_param;
    @@

    long round_rate_name(struct clk_hw *hw_param, unsigned long rate_param,
                  unsigned long *parent_rate_param)
    {
    	...
    }

    // Rename the route_rate function name to determine_rate()
    @ script:python generate_name depends on has_round_rate @
    round_rate_name << has_round_rate.round_rate_name;
    new_name;
    @@

    coccinelle.new_name = round_rate_name.replace("_round_rate", "_determine_rate")

    // Change rate to req->rate; also change occurrences of 'return XXX'.
    @ chg_rate depends on generate_name @
    identifier has_round_rate.round_rate_name;
    identifier has_round_rate.hw_param;
    identifier has_round_rate.rate_param;
    identifier has_round_rate.parent_rate_param;
    identifier ERR =~ "E.*";
    expression E;
    @@

    long round_rate_name(struct clk_hw *hw_param, unsigned long rate_param,
                  unsigned long *parent_rate_param)
    {
    <...
    (
    -return -ERR;
    +return -ERR;
    |
    - return rate_param;
    + return 0;
    |
    - return E;
    + req->rate = E;
    +
    + return 0;
    |
    - rate_param
    + req->rate
    )
    ...>
    }

    // Coccinelle only transforms the first occurrence of the rate parameter
    // Run a second time. FIXME: Is there a better way to do this?
    @ chg_rate2 depends on generate_name @
    identifier has_round_rate.round_rate_name;
    identifier has_round_rate.hw_param;
    identifier has_round_rate.rate_param;
    identifier has_round_rate.parent_rate_param;
    @@

    long round_rate_name(struct clk_hw *hw_param, unsigned long rate_param,
                  unsigned long *parent_rate_param)
    {
    <...
    - rate_param
    + req->rate
    ...>
    }

    // Change parent_rate to req->best_parent_rate
    @ chg_parent_rate depends on generate_name @
    identifier has_round_rate.round_rate_name;
    identifier has_round_rate.hw_param;
    identifier has_round_rate.rate_param;
    identifier has_round_rate.parent_rate_param;
    @@

    long round_rate_name(struct clk_hw *hw_param, unsigned long rate_param,
                  unsigned long *parent_rate_param)
    {
    <...
    (
    - *parent_rate_param
    + req->best_parent_rate
    |
    - parent_rate_param
    + &req->best_parent_rate
    )
    ...>
    }

    // Convert the function definition from round_rate() to determine_rate()
    @ func_definition depends on chg_rate @
    identifier has_round_rate.round_rate_name;
    identifier has_round_rate.hw_param;
    identifier has_round_rate.rate_param;
    identifier has_round_rate.parent_rate_param;
    identifier generate_name.new_name;
    @@

    - long round_rate_name(struct clk_hw *hw_param, unsigned long rate_param,
    -               unsigned long *parent_rate_param)
    + int new_name(struct clk_hw *hw, struct clk_rate_request *req)
    {
        ...
    }

    // Update the ops from round_rate() to determine_rate()
    @ ops depends on func_definition @
    identifier has_round_rate.round_rate_name;
    identifier generate_name.new_name;
    @@

    {
        ...,
    -   .round_rate = round_rate_name,
    +   .determine_rate = new_name,
        ...,
    }

Note that I used coccinelle 1.2 instead of 1.3 since the newer version
adds unnecessary braces as described in this post.
https://lore.kernel.org/cocci/67642477-5f3e-4b2a-914d-579a54f48cbd@intel.com/
parents bfd29127 d5f317fd
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+34 −30
Original line number Diff line number Diff line
@@ -1982,8 +1982,8 @@ static unsigned long da7219_wclk_recalc_rate(struct clk_hw *hw,
	}
}

static long da7219_wclk_round_rate(struct clk_hw *hw, unsigned long rate,
				   unsigned long *parent_rate)
static int da7219_wclk_determine_rate(struct clk_hw *hw,
				      struct clk_rate_request *req)
{
	struct da7219_priv *da7219 =
		container_of(hw, struct da7219_priv,
@@ -1992,28 +1992,30 @@ static long da7219_wclk_round_rate(struct clk_hw *hw, unsigned long rate,
	if (!da7219->master)
		return -EINVAL;

	if (rate < 11025)
		return 8000;
	else if (rate < 12000)
		return 11025;
	else if (rate < 16000)
		return 12000;
	else if (rate < 22050)
		return 16000;
	else if (rate < 24000)
		return 22050;
	else if (rate < 32000)
		return 24000;
	else if (rate < 44100)
		return 32000;
	else if (rate < 48000)
		return 44100;
	else if (rate < 88200)
		return 48000;
	else if (rate < 96000)
		return 88200;
	if (req->rate < 11025)
		req->rate = 8000;
	else if (req->rate < 12000)
		req->rate = 11025;
	else if (req->rate < 16000)
		req->rate = 12000;
	else if (req->rate < 22050)
		req->rate = 16000;
	else if (req->rate < 24000)
		req->rate = 22050;
	else if (req->rate < 32000)
		req->rate = 24000;
	else if (req->rate < 44100)
		req->rate = 32000;
	else if (req->rate < 48000)
		req->rate = 44100;
	else if (req->rate < 88200)
		req->rate = 48000;
	else if (req->rate < 96000)
		req->rate = 88200;
	else
		return 96000;
		req->rate = 96000;

	return 0;
}

static int da7219_wclk_set_rate(struct clk_hw *hw, unsigned long rate,
@@ -2070,15 +2072,15 @@ static unsigned long da7219_bclk_get_factor(unsigned long rate,
		return 256;
}

static long da7219_bclk_round_rate(struct clk_hw *hw, unsigned long rate,
				   unsigned long *parent_rate)
static int da7219_bclk_determine_rate(struct clk_hw *hw,
				      struct clk_rate_request *req)
{
	struct da7219_priv *da7219 =
		container_of(hw, struct da7219_priv,
			     dai_clks_hw[DA7219_DAI_BCLK_IDX]);
	unsigned long factor;

	if (!*parent_rate || !da7219->master)
	if (!req->best_parent_rate || !da7219->master)
		return -EINVAL;

	/*
@@ -2088,9 +2090,11 @@ static long da7219_bclk_round_rate(struct clk_hw *hw, unsigned long rate,
	 * parent WCLK rate set and find the appropriate multiplier of BCLK to
	 * get the rounded down BCLK value.
	 */
	factor = da7219_bclk_get_factor(rate, *parent_rate);
	factor = da7219_bclk_get_factor(req->rate, req->best_parent_rate);

	req->rate = req->best_parent_rate * factor;

	return *parent_rate * factor;
	return 0;
}

static int da7219_bclk_set_rate(struct clk_hw *hw, unsigned long rate,
@@ -2116,12 +2120,12 @@ static const struct clk_ops da7219_dai_clk_ops[DA7219_DAI_NUM_CLKS] = {
		.unprepare = da7219_wclk_unprepare,
		.is_prepared = da7219_wclk_is_prepared,
		.recalc_rate = da7219_wclk_recalc_rate,
		.round_rate = da7219_wclk_round_rate,
		.determine_rate = da7219_wclk_determine_rate,
		.set_rate = da7219_wclk_set_rate,
	},
	[DA7219_DAI_BCLK_IDX] = {
		.recalc_rate = da7219_bclk_recalc_rate,
		.round_rate = da7219_bclk_round_rate,
		.determine_rate = da7219_bclk_determine_rate,
		.set_rate = da7219_bclk_set_rate,
	},
};
+14 −12
Original line number Diff line number Diff line
@@ -2675,8 +2675,8 @@ static unsigned long rt5682_wclk_recalc_rate(struct clk_hw *hw,
	return rt5682->lrck[RT5682_AIF1];
}

static long rt5682_wclk_round_rate(struct clk_hw *hw, unsigned long rate,
				   unsigned long *parent_rate)
static int rt5682_wclk_determine_rate(struct clk_hw *hw,
				      struct clk_rate_request *req)
{
	struct rt5682_priv *rt5682 =
		container_of(hw, struct rt5682_priv,
@@ -2689,13 +2689,13 @@ static long rt5682_wclk_round_rate(struct clk_hw *hw, unsigned long rate,
	 * Only accept to set wclk rate to 44.1k or 48kHz.
	 * It will force to 48kHz if not both.
	 */
	if (rate != CLK_48 && rate != CLK_44) {
	if (req->rate != CLK_48 && req->rate != CLK_44) {
		dev_warn(rt5682->i2c_dev, "%s: clk %s only support %d or %d Hz output\n",
			__func__, clk_name, CLK_44, CLK_48);
		rate = CLK_48;
		req->rate = CLK_48;
	}

	return rate;
	return 0;
}

static int rt5682_wclk_set_rate(struct clk_hw *hw, unsigned long rate,
@@ -2795,15 +2795,15 @@ static unsigned long rt5682_bclk_get_factor(unsigned long rate,
		return 256;
}

static long rt5682_bclk_round_rate(struct clk_hw *hw, unsigned long rate,
				   unsigned long *parent_rate)
static int rt5682_bclk_determine_rate(struct clk_hw *hw,
				      struct clk_rate_request *req)
{
	struct rt5682_priv *rt5682 =
		container_of(hw, struct rt5682_priv,
			     dai_clks_hw[RT5682_DAI_BCLK_IDX]);
	unsigned long factor;

	if (!*parent_rate || !rt5682_clk_check(rt5682))
	if (!req->best_parent_rate || !rt5682_clk_check(rt5682))
		return -EINVAL;

	/*
@@ -2813,9 +2813,11 @@ static long rt5682_bclk_round_rate(struct clk_hw *hw, unsigned long rate,
	 * and find the appropriate multiplier of BCLK to
	 * get the rounded down BCLK value.
	 */
	factor = rt5682_bclk_get_factor(rate, *parent_rate);
	factor = rt5682_bclk_get_factor(req->rate, req->best_parent_rate);

	req->rate = req->best_parent_rate * factor;

	return *parent_rate * factor;
	return 0;
}

static int rt5682_bclk_set_rate(struct clk_hw *hw, unsigned long rate,
@@ -2849,12 +2851,12 @@ static const struct clk_ops rt5682_dai_clk_ops[RT5682_DAI_NUM_CLKS] = {
		.prepare = rt5682_wclk_prepare,
		.unprepare = rt5682_wclk_unprepare,
		.recalc_rate = rt5682_wclk_recalc_rate,
		.round_rate = rt5682_wclk_round_rate,
		.determine_rate = rt5682_wclk_determine_rate,
		.set_rate = rt5682_wclk_set_rate,
	},
	[RT5682_DAI_BCLK_IDX] = {
		.recalc_rate = rt5682_bclk_recalc_rate,
		.round_rate = rt5682_bclk_round_rate,
		.determine_rate = rt5682_bclk_determine_rate,
		.set_rate = rt5682_bclk_set_rate,
	},
};
+14 −12
Original line number Diff line number Diff line
@@ -2610,8 +2610,8 @@ static unsigned long rt5682s_wclk_recalc_rate(struct clk_hw *hw,
	return rt5682s->lrck[RT5682S_AIF1];
}

static long rt5682s_wclk_round_rate(struct clk_hw *hw, unsigned long rate,
				   unsigned long *parent_rate)
static int rt5682s_wclk_determine_rate(struct clk_hw *hw,
				       struct clk_rate_request *req)
{
	struct rt5682s_priv *rt5682s =
		container_of(hw, struct rt5682s_priv, dai_clks_hw[RT5682S_DAI_WCLK_IDX]);
@@ -2624,13 +2624,13 @@ static long rt5682s_wclk_round_rate(struct clk_hw *hw, unsigned long rate,
	 * Only accept to set wclk rate to 44.1k or 48kHz.
	 * It will force to 48kHz if not both.
	 */
	if (rate != CLK_48 && rate != CLK_44) {
	if (req->rate != CLK_48 && req->rate != CLK_44) {
		dev_warn(component->dev, "%s: clk %s only support %d or %d Hz output\n",
			__func__, clk_name, CLK_44, CLK_48);
		rate = CLK_48;
		req->rate = CLK_48;
	}

	return rate;
	return 0;
}

static int rt5682s_wclk_set_rate(struct clk_hw *hw, unsigned long rate,
@@ -2719,14 +2719,14 @@ static unsigned long rt5682s_bclk_get_factor(unsigned long rate,
		return 256;
}

static long rt5682s_bclk_round_rate(struct clk_hw *hw, unsigned long rate,
				   unsigned long *parent_rate)
static int rt5682s_bclk_determine_rate(struct clk_hw *hw,
				       struct clk_rate_request *req)
{
	struct rt5682s_priv *rt5682s =
		container_of(hw, struct rt5682s_priv, dai_clks_hw[RT5682S_DAI_BCLK_IDX]);
	unsigned long factor;

	if (!*parent_rate || !rt5682s_clk_check(rt5682s))
	if (!req->best_parent_rate || !rt5682s_clk_check(rt5682s))
		return -EINVAL;

	/*
@@ -2736,9 +2736,11 @@ static long rt5682s_bclk_round_rate(struct clk_hw *hw, unsigned long rate,
	 * and find the appropriate multiplier of BCLK to
	 * get the rounded down BCLK value.
	 */
	factor = rt5682s_bclk_get_factor(rate, *parent_rate);
	factor = rt5682s_bclk_get_factor(req->rate, req->best_parent_rate);

	req->rate = req->best_parent_rate * factor;

	return *parent_rate * factor;
	return 0;
}

static int rt5682s_bclk_set_rate(struct clk_hw *hw, unsigned long rate,
@@ -2769,12 +2771,12 @@ static const struct clk_ops rt5682s_dai_clk_ops[RT5682S_DAI_NUM_CLKS] = {
		.prepare = rt5682s_wclk_prepare,
		.unprepare = rt5682s_wclk_unprepare,
		.recalc_rate = rt5682s_wclk_recalc_rate,
		.round_rate = rt5682s_wclk_round_rate,
		.determine_rate = rt5682s_wclk_determine_rate,
		.set_rate = rt5682s_wclk_set_rate,
	},
	[RT5682S_DAI_BCLK_IDX] = {
		.recalc_rate = rt5682s_bclk_recalc_rate,
		.round_rate = rt5682s_bclk_round_rate,
		.determine_rate = rt5682s_bclk_determine_rate,
		.set_rate = rt5682s_bclk_set_rate,
	},
};
+4 −4
Original line number Diff line number Diff line
@@ -69,17 +69,17 @@ static unsigned long clk_q6dsp_recalc_rate(struct clk_hw *hw,
	return clk->rate;
}

static long clk_q6dsp_round_rate(struct clk_hw *hw, unsigned long rate,
				 unsigned long *parent_rate)
static int clk_q6dsp_determine_rate(struct clk_hw *hw,
				    struct clk_rate_request *req)
{
	return rate;
	return 0;
}

static const struct clk_ops clk_q6dsp_ops = {
	.prepare	= clk_q6dsp_prepare,
	.unprepare	= clk_q6dsp_unprepare,
	.set_rate	= clk_q6dsp_set_rate,
	.round_rate	= clk_q6dsp_round_rate,
	.determine_rate = clk_q6dsp_determine_rate,
	.recalc_rate	= clk_q6dsp_recalc_rate,
};

+13 −8
Original line number Diff line number Diff line
@@ -461,20 +461,25 @@ static int stm32_i2s_set_parent_rate(struct stm32_i2s_data *i2s,
	return -EINVAL;
}

static long stm32_i2smclk_round_rate(struct clk_hw *hw, unsigned long rate,
				     unsigned long *prate)
static int stm32_i2smclk_determine_rate(struct clk_hw *hw,
					struct clk_rate_request *req)
{
	struct stm32_i2smclk_data *mclk = to_mclk_data(hw);
	struct stm32_i2s_data *i2s = mclk->i2s_data;
	int ret;

	ret = stm32_i2s_calc_clk_div(i2s, *prate, rate);
	if (ret)
		return ret;
	ret = stm32_i2s_calc_clk_div(i2s, req->best_parent_rate, req->rate);
	if (ret) {
		req->rate = ret;

	mclk->freq = *prate / i2s->divider;
		return 0;
	}

	return mclk->freq;
	mclk->freq = req->best_parent_rate / i2s->divider;

	req->rate = mclk->freq;

	return 0;
}

static unsigned long stm32_i2smclk_recalc_rate(struct clk_hw *hw,
@@ -530,7 +535,7 @@ static const struct clk_ops mclk_ops = {
	.enable = stm32_i2smclk_enable,
	.disable = stm32_i2smclk_disable,
	.recalc_rate = stm32_i2smclk_recalc_rate,
	.round_rate = stm32_i2smclk_round_rate,
	.determine_rate = stm32_i2smclk_determine_rate,
	.set_rate = stm32_i2smclk_set_rate,
};

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