Commit dd86a1d0 authored by Borislav Petkov (AMD)'s avatar Borislav Petkov (AMD) Committed by Ingo Molnar
Browse files

x86/bugs: Remove X86_BUG_MMIO_UNKNOWN 



Whack this thing because:

- the "unknown" handling is done only for this vuln and not for the
  others

- it doesn't do anything besides reporting things differently. It
  doesn't apply any mitigations - it is simply causing unnecessary
  complications to the code which don't bring anything besides
  maintenance overhead to what is already a very nasty spaghetti pile

- all the currently unaffected CPUs can also be in "unknown" status so
  there's no need for special handling here

so get rid of it.

Signed-off-by: default avatarBorislav Petkov (AMD) <bp@alien8.de>
Signed-off-by: default avatarIngo Molnar <mingo@kernel.org>
Cc: Andrew Cooper <andrew.cooper3@citrix.com>
Cc: David Kaplan <david.kaplan@amd.com>
Cc: H. Peter Anvin <hpa@zytor.com>
Cc: Josh Poimboeuf <jpoimboe@redhat.com>
Cc: Pawan Gupta <pawan.kumar.gupta@linux.intel.com>
Link: https://lore.kernel.org/r/20250414150951.5345-1-bp@kernel.org
parent 9fb6938d

arch/x86/include/asm/cpufeatures.h

+1 −1
Original line number Diff line number Diff line
@@ -519,7 +519,7 @@ 
#define X86_BUG_ITLB_MULTIHIT		X86_BUG(23) /* "itlb_multihit" CPU may incur MCE during certain page attribute changes */

#define X86_BUG_SRBDS			X86_BUG(24) /* "srbds" CPU may leak RNG bits if not mitigated */

#define X86_BUG_MMIO_STALE_DATA		X86_BUG(25) /* "mmio_stale_data" CPU is affected by Processor MMIO Stale Data vulnerabilities */

#define X86_BUG_MMIO_UNKNOWN		X86_BUG(26) /* "mmio_unknown" CPU is too old and its MMIO Stale Data status is unknown */

/* unused, was #define X86_BUG_MMIO_UNKNOWN		X86_BUG(26) "mmio_unknown" CPU is too old and its MMIO Stale Data status is unknown */

#define X86_BUG_RETBLEED		X86_BUG(27) /* "retbleed" CPU is affected by RETBleed */

#define X86_BUG_EIBRS_PBRSB		X86_BUG(28) /* "eibrs_pbrsb" EIBRS is vulnerable to Post Barrier RSB Predictions */

#define X86_BUG_SMT_RSB			X86_BUG(29) /* "smt_rsb" CPU is vulnerable to Cross-Thread Return Address Predictions */

arch/x86/kernel/cpu/bugs.c

+1 −11
Original line number Diff line number Diff line
@@ -428,7 +428,6 @@ static const char * const mmio_strings[] = { 
static void __init mmio_select_mitigation(void)

{

	if (!boot_cpu_has_bug(X86_BUG_MMIO_STALE_DATA) ||

	     boot_cpu_has_bug(X86_BUG_MMIO_UNKNOWN) ||

	     cpu_mitigations_off()) {

		mmio_mitigation = MMIO_MITIGATION_OFF;

		return;
@@ -591,8 +590,6 @@ static void __init md_clear_update_mitigation(void) 
		pr_info("TAA: %s\n", taa_strings[taa_mitigation]);

	if (boot_cpu_has_bug(X86_BUG_MMIO_STALE_DATA))

		pr_info("MMIO Stale Data: %s\n", mmio_strings[mmio_mitigation]);

	else if (boot_cpu_has_bug(X86_BUG_MMIO_UNKNOWN))

		pr_info("MMIO Stale Data: Unknown: No mitigations\n");

	if (boot_cpu_has_bug(X86_BUG_RFDS))

		pr_info("Register File Data Sampling: %s\n", rfds_strings[rfds_mitigation]);

}
@@ -2819,9 +2816,6 @@ static ssize_t tsx_async_abort_show_state(char *buf) 


static ssize_t mmio_stale_data_show_state(char *buf)

{

	if (boot_cpu_has_bug(X86_BUG_MMIO_UNKNOWN))

		return sysfs_emit(buf, "Unknown: No mitigations\n");



	if (mmio_mitigation == MMIO_MITIGATION_OFF)

		return sysfs_emit(buf, "%s\n", mmio_strings[mmio_mitigation]);
@@ -3006,7 +3000,6 @@ static ssize_t cpu_show_common(struct device *dev, struct device_attribute *attr 
		return srbds_show_state(buf);



	case X86_BUG_MMIO_STALE_DATA:

	case X86_BUG_MMIO_UNKNOWN:

		return mmio_stale_data_show_state(buf);



	case X86_BUG_RETBLEED:
@@ -3075,9 +3068,6 @@ ssize_t cpu_show_srbds(struct device *dev, struct device_attribute *attr, char * 


ssize_t cpu_show_mmio_stale_data(struct device *dev, struct device_attribute *attr, char *buf)

{

	if (boot_cpu_has_bug(X86_BUG_MMIO_UNKNOWN))

		return cpu_show_common(dev, attr, buf, X86_BUG_MMIO_UNKNOWN);

	else

	return cpu_show_common(dev, attr, buf, X86_BUG_MMIO_STALE_DATA);

}

arch/x86/kernel/cpu/common.c

+0 −5
Original line number Diff line number Diff line
@@ -1402,15 +1402,10 @@ static void __init cpu_set_bug_bits(struct cpuinfo_x86 *c) 
	 * Affected CPU list is generally enough to enumerate the vulnerability,

	 * but for virtualization case check for ARCH_CAP MSR bits also, VMM may

	 * not want the guest to enumerate the bug.

	 *

	 * Set X86_BUG_MMIO_UNKNOWN for CPUs that are neither in the blacklist,

	 * nor in the whitelist and also don't enumerate MSR ARCH_CAP MMIO bits.

	 */

	if (!arch_cap_mmio_immune(x86_arch_cap_msr)) {

		if (cpu_matches(cpu_vuln_blacklist, MMIO))

			setup_force_cpu_bug(X86_BUG_MMIO_STALE_DATA);

		else if (!cpu_matches(cpu_vuln_whitelist, NO_MMIO))

			setup_force_cpu_bug(X86_BUG_MMIO_UNKNOWN);

	}



	if (!cpu_has(c, X86_FEATURE_BTC_NO)) {

tools/arch/x86/include/asm/cpufeatures.h

+1 −1
Original line number Diff line number Diff line
@@ -508,7 +508,7 @@ 
#define X86_BUG_ITLB_MULTIHIT		X86_BUG(23) /* "itlb_multihit" CPU may incur MCE during certain page attribute changes */

#define X86_BUG_SRBDS			X86_BUG(24) /* "srbds" CPU may leak RNG bits if not mitigated */

#define X86_BUG_MMIO_STALE_DATA		X86_BUG(25) /* "mmio_stale_data" CPU is affected by Processor MMIO Stale Data vulnerabilities */

#define X86_BUG_MMIO_UNKNOWN		X86_BUG(26) /* "mmio_unknown" CPU is too old and its MMIO Stale Data status is unknown */

/* unused, was #define X86_BUG_MMIO_UNKNOWN		X86_BUG(26) * "mmio_unknown" CPU is too old and its MMIO Stale Data status is unknown */

#define X86_BUG_RETBLEED		X86_BUG(27) /* "retbleed" CPU is affected by RETBleed */

#define X86_BUG_EIBRS_PBRSB		X86_BUG(28) /* "eibrs_pbrsb" EIBRS is vulnerable to Post Barrier RSB Predictions */

#define X86_BUG_SMT_RSB			X86_BUG(29) /* "smt_rsb" CPU is vulnerable to Cross-Thread Return Address Predictions */