Unverified Commit dd8a9807 authored by Andy Shevchenko's avatar Andy Shevchenko Committed by Mark Brown
Browse files

spi: Group CS related fields in struct spi_device 



The CS related fields are sparse in the struct spi_device. Group them.
While at it, fix the comment style of cs_index_mask.

Signed-off-by: default avatarAndy Shevchenko <andriy.shevchenko@linux.intel.com>
Link: https://patch.msgid.link/20250331103609.4160281-1-andriy.shevchenko@linux.intel.com


Signed-off-by: default avatarMark Brown <broonie@kernel.org>
parent 0af2f6be

include/linux/spi/spi.h

+21 −16
Original line number Diff line number Diff line
@@ -136,13 +136,6 @@ extern void spi_transfer_cs_change_delay_exec(struct spi_message *msg, 
 * @max_speed_hz: Maximum clock rate to be used with this chip

 *	(on this board); may be changed by the device's driver.

 *	The spi_transfer.speed_hz can override this for each transfer.

 * @chip_select: Array of physical chipselect, spi->chipselect[i] gives

 *	the corresponding physical CS for logical CS i.

 * @mode: The spi mode defines how data is clocked out and in.

 *	This may be changed by the device's driver.

 *	The "active low" default for chipselect mode can be overridden

 *	(by specifying SPI_CS_HIGH) as can the "MSB first" default for

 *	each word in a transfer (by specifying SPI_LSB_FIRST).

 * @bits_per_word: Data transfers involve one or more words; word sizes

 *	like eight or 12 bits are common.  In-memory wordsizes are

 *	powers of two bytes (e.g. 20 bit samples use 32 bits).
@@ -150,6 +143,11 @@ extern void spi_transfer_cs_change_delay_exec(struct spi_message *msg, 
 *	default (0) indicating protocol words are eight bit bytes.

 *	The spi_transfer.bits_per_word can override this for each transfer.

 * @rt: Make the pump thread real time priority.

 * @mode: The spi mode defines how data is clocked out and in.

 *	This may be changed by the device's driver.

 *	The "active low" default for chipselect mode can be overridden

 *	(by specifying SPI_CS_HIGH) as can the "MSB first" default for

 *	each word in a transfer (by specifying SPI_LSB_FIRST).

 * @irq: Negative, or the number passed to request_irq() to receive

 *	interrupts from this device.

 * @controller_state: Controller's runtime state
@@ -162,8 +160,7 @@ extern void spi_transfer_cs_change_delay_exec(struct spi_message *msg, 
 *	the device will bind to the named driver and only the named driver.

 *	Do not set directly, because core frees it; use driver_set_override() to

 *	set or clear it.

 * @cs_gpiod: Array of GPIO descriptors of the corresponding chipselect lines

 *	(optional, NULL when not using a GPIO line)

 * @pcpu_statistics: statistics for the spi_device

 * @word_delay: delay to be inserted between consecutive

 *	words of a transfer

 * @cs_setup: delay to be introduced by the controller after CS is asserted
@@ -171,8 +168,11 @@ extern void spi_transfer_cs_change_delay_exec(struct spi_message *msg, 
 * @cs_inactive: delay to be introduced by the controller after CS is

 *	deasserted. If @cs_change_delay is used from @spi_transfer, then the

 *	two delays will be added up.

 * @pcpu_statistics: statistics for the spi_device

 * @chip_select: Array of physical chipselect, spi->chipselect[i] gives

 *	the corresponding physical CS for logical CS i.

 * @cs_index_mask: Bit mask of the active chipselect(s) in the chipselect array

 * @cs_gpiod: Array of GPIO descriptors of the corresponding chipselect lines

 *	(optional, NULL when not using a GPIO line)

 *

 * A @spi_device is used to interchange data between an SPI target device

 * (usually a discrete chip) and CPU memory.
@@ -187,7 +187,6 @@ struct spi_device { 
	struct device		dev;

	struct spi_controller	*controller;

	u32			max_speed_hz;

	u8			chip_select[SPI_CS_CNT_MAX];

	u8			bits_per_word;

	bool			rt;

#define SPI_NO_TX		BIT(31)		/* No transmit wire */
@@ -218,23 +217,29 @@ struct spi_device { 
	void			*controller_data;

	char			modalias[SPI_NAME_SIZE];

	const char		*driver_override;

	struct gpio_desc	*cs_gpiod[SPI_CS_CNT_MAX];	/* Chip select gpio desc */



	/* The statistics */

	struct spi_statistics __percpu	*pcpu_statistics;



	struct spi_delay	word_delay; /* Inter-word delay */



	/* CS delays */

	struct spi_delay	cs_setup;

	struct spi_delay	cs_hold;

	struct spi_delay	cs_inactive;



	/* The statistics */

	struct spi_statistics __percpu	*pcpu_statistics;

	u8			chip_select[SPI_CS_CNT_MAX];



	/* Bit mask of the chipselect(s) that the driver need to use from

	/*

	 * Bit mask of the chipselect(s) that the driver need to use from

	 * the chipselect array. When the controller is capable to handle

	 * multiple chip selects & memories are connected in parallel

	 * then more than one bit need to be set in cs_index_mask.

	 */

	u32			cs_index_mask : SPI_CS_CNT_MAX;



	struct gpio_desc	*cs_gpiod[SPI_CS_CNT_MAX];	/* Chip select gpio desc */



	/*

	 * Likely need more hooks for more protocol options affecting how

	 * the controller talks to each chip, like: