Commit ddbf63b2 authored by Kever Yang's avatar Kever Yang Committed by Heiko Stuebner
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arm64: dts: rockchip: Add rk3576 naneng combphy nodes 



rk3576 has two naneng combo phys:
- combophy0 is used for one of pcie and sata;
- combophy1 is used for one of pcie, sata and usb3;

Signed-off-by: default avatarKever Yang <kever.yang@rock-chips.com>
Link: https://lore.kernel.org/r/20250107074911.550057-2-kever.yang@rock-chips.com


Signed-off-by: default avatarHeiko Stuebner <heiko@sntech.de>
parent 39b771a8

arch/arm64/boot/dts/rockchip/rk3576.dtsi

+36 −0
Original line number Diff line number Diff line
@@ -1587,6 +1587,42 @@ uart11: serial@2afd0000 { 
			status = "disabled";

		};



		combphy0_ps: phy@2b050000 {

			compatible = "rockchip,rk3576-naneng-combphy";

			reg = <0x0 0x2b050000 0x0 0x100>;

			#phy-cells = <1>;

			clocks = <&cru CLK_REF_PCIE0_PHY>,

				 <&cru PCLK_PCIE2_COMBOPHY0>,

				 <&cru PCLK_PCIE0>;

			clock-names = "ref", "apb", "pipe";

			assigned-clocks = <&cru CLK_REF_PCIE0_PHY>;

			assigned-clock-rates = <100000000>;

			resets = <&cru SRST_PCIE0_PIPE_PHY>,

				 <&cru SRST_P_PCIE2_COMBOPHY0>;

			reset-names = "phy", "apb";

			rockchip,pipe-grf = <&php_grf>;

			rockchip,pipe-phy-grf = <&pipe_phy0_grf>;

			status = "disabled";

		};



		combphy1_psu: phy@2b060000 {

			compatible = "rockchip,rk3576-naneng-combphy";

			reg = <0x0 0x2b060000 0x0 0x100>;

			#phy-cells = <1>;

			clocks = <&cru CLK_REF_PCIE1_PHY>,

				 <&cru PCLK_PCIE2_COMBOPHY1>,

				 <&cru PCLK_PCIE1>;

			clock-names = "ref", "apb", "pipe";

			assigned-clocks = <&cru CLK_REF_PCIE1_PHY>;

			assigned-clock-rates = <100000000>;

			resets = <&cru SRST_PCIE1_PIPE_PHY>,

				 <&cru SRST_P_PCIE2_COMBOPHY1>;

			reset-names = "phy", "apb";

			rockchip,pipe-grf = <&php_grf>;

			rockchip,pipe-phy-grf = <&pipe_phy1_grf>;

			status = "disabled";

		};



		sram: sram@3ff88000 {

			compatible = "mmio-sram";

			reg = <0x0 0x3ff88000 0x0 0x78000>;