Commit ddcc2f61 authored by Claudiu Beznea's avatar Claudiu Beznea Committed by Geert Uytterhoeven
Browse files

clk: renesas: rzg2l-cpg: Use GENPD_FLAG_* flags instead of local ones 



For watchdog PM domain it is necessary to provide GENPD_FLAG_IRQ_SAFE flag
to be able to power on the watchdog PM domain from atomic context. For
this, adjust the current infrastructure to be able to provide GENPD_FLAG_*
for individual PM domains.

With this, remove the always_on flag from rzg2l_cpg_add_pm_domains() as
it is not necessary anymore.

Signed-off-by: default avatarClaudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
Reviewed-by: default avatarGeert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: default avatarUlf Hansson <ulf.hansson@linaro.org>
Link: https://lore.kernel.org/20241015164732.4085249-3-claudiu.beznea.uj@bp.renesas.com


Signed-off-by: default avatarGeert Uytterhoeven <geert+renesas@glider.be>
parent b739073a

drivers/clk/renesas/r9a08g045-cpg.c

+20 −33
Original line number Diff line number Diff line
@@ -9,6 +9,7 @@ 
#include <linux/device.h>

#include <linux/init.h>

#include <linux/kernel.h>

#include <linux/pm_domain.h>



#include <dt-bindings/clock/r9a08g045-cpg.h>
@@ -266,61 +267,47 @@ static const struct rzg2l_cpg_pm_domain_init_data r9a08g045_pm_domains[] = { 
	/* Keep always-on domain on the first position for proper domains registration. */

	DEF_PD("always-on",	R9A08G045_PD_ALWAYS_ON,

				DEF_REG_CONF(0, 0),

				RZG2L_PD_F_ALWAYS_ON),

				GENPD_FLAG_ALWAYS_ON),

	DEF_PD("gic",		R9A08G045_PD_GIC,

				DEF_REG_CONF(CPG_BUS_ACPU_MSTOP, BIT(3)),

				RZG2L_PD_F_ALWAYS_ON),

				GENPD_FLAG_ALWAYS_ON),

	DEF_PD("ia55",		R9A08G045_PD_IA55,

				DEF_REG_CONF(CPG_BUS_PERI_CPU_MSTOP, BIT(13)),

				RZG2L_PD_F_ALWAYS_ON),

				GENPD_FLAG_ALWAYS_ON),

	DEF_PD("dmac",		R9A08G045_PD_DMAC,

				DEF_REG_CONF(CPG_BUS_REG1_MSTOP, GENMASK(3, 0)),

				RZG2L_PD_F_ALWAYS_ON),

				GENPD_FLAG_ALWAYS_ON),

	DEF_PD("wdt0",		R9A08G045_PD_WDT0,

				DEF_REG_CONF(CPG_BUS_REG0_MSTOP, BIT(0)),

				RZG2L_PD_F_NONE),

				DEF_REG_CONF(CPG_BUS_REG0_MSTOP, BIT(0)), 0),

	DEF_PD("sdhi0",		R9A08G045_PD_SDHI0,

				DEF_REG_CONF(CPG_BUS_PERI_COM_MSTOP, BIT(0)),

				RZG2L_PD_F_NONE),

				DEF_REG_CONF(CPG_BUS_PERI_COM_MSTOP, BIT(0)), 0),

	DEF_PD("sdhi1",		R9A08G045_PD_SDHI1,

				DEF_REG_CONF(CPG_BUS_PERI_COM_MSTOP, BIT(1)),

				RZG2L_PD_F_NONE),

				DEF_REG_CONF(CPG_BUS_PERI_COM_MSTOP, BIT(1)), 0),

	DEF_PD("sdhi2",		R9A08G045_PD_SDHI2,

				DEF_REG_CONF(CPG_BUS_PERI_COM_MSTOP, BIT(11)),

				RZG2L_PD_F_NONE),

				DEF_REG_CONF(CPG_BUS_PERI_COM_MSTOP, BIT(11)), 0),

	DEF_PD("usb0",		R9A08G045_PD_USB0,

				DEF_REG_CONF(CPG_BUS_PERI_COM_MSTOP, GENMASK(6, 5)),

				RZG2L_PD_F_NONE),

				DEF_REG_CONF(CPG_BUS_PERI_COM_MSTOP, GENMASK(6, 5)), 0),

	DEF_PD("usb1",		R9A08G045_PD_USB1,

				DEF_REG_CONF(CPG_BUS_PERI_COM_MSTOP, BIT(7)),

				RZG2L_PD_F_NONE),

				DEF_REG_CONF(CPG_BUS_PERI_COM_MSTOP, BIT(7)), 0),

	DEF_PD("usb-phy",	R9A08G045_PD_USB_PHY,

				DEF_REG_CONF(CPG_BUS_PERI_COM_MSTOP, BIT(4)),

				RZG2L_PD_F_NONE),

				DEF_REG_CONF(CPG_BUS_PERI_COM_MSTOP, BIT(4)), 0),

	DEF_PD("eth0",		R9A08G045_PD_ETHER0,

				DEF_REG_CONF(CPG_BUS_PERI_COM_MSTOP, BIT(2)),

				RZG2L_PD_F_NONE),

				DEF_REG_CONF(CPG_BUS_PERI_COM_MSTOP, BIT(2)), 0),

	DEF_PD("eth1",		R9A08G045_PD_ETHER1,

				DEF_REG_CONF(CPG_BUS_PERI_COM_MSTOP, BIT(3)),

				RZG2L_PD_F_NONE),

				DEF_REG_CONF(CPG_BUS_PERI_COM_MSTOP, BIT(3)), 0),

	DEF_PD("i2c0",		R9A08G045_PD_I2C0,

				DEF_REG_CONF(CPG_BUS_MCPU2_MSTOP, BIT(10)),

				RZG2L_PD_F_NONE),

				DEF_REG_CONF(CPG_BUS_MCPU2_MSTOP, BIT(10)), 0),

	DEF_PD("i2c1",		R9A08G045_PD_I2C1,

				DEF_REG_CONF(CPG_BUS_MCPU2_MSTOP, BIT(11)),

				RZG2L_PD_F_NONE),

				DEF_REG_CONF(CPG_BUS_MCPU2_MSTOP, BIT(11)), 0),

	DEF_PD("i2c2",		R9A08G045_PD_I2C2,

				DEF_REG_CONF(CPG_BUS_MCPU2_MSTOP, BIT(12)),

				RZG2L_PD_F_NONE),

				DEF_REG_CONF(CPG_BUS_MCPU2_MSTOP, BIT(12)), 0),

	DEF_PD("i2c3",		R9A08G045_PD_I2C3,

				DEF_REG_CONF(CPG_BUS_MCPU2_MSTOP, BIT(13)),

				RZG2L_PD_F_NONE),

				DEF_REG_CONF(CPG_BUS_MCPU2_MSTOP, BIT(13)), 0),

	DEF_PD("scif0",		R9A08G045_PD_SCIF0,

				DEF_REG_CONF(CPG_BUS_MCPU2_MSTOP, BIT(1)),

				RZG2L_PD_F_NONE),

				DEF_REG_CONF(CPG_BUS_MCPU2_MSTOP, BIT(1)), 0),

	DEF_PD("vbat",		R9A08G045_PD_VBAT,

				DEF_REG_CONF(CPG_BUS_MCPU3_MSTOP, BIT(8)),

				RZG2L_PD_F_ALWAYS_ON),

				GENPD_FLAG_ALWAYS_ON),

};



const struct rzg2l_cpg_info r9a08g045_cpg_info = {

drivers/clk/renesas/rzg2l-cpg.c

+1 −3
Original line number Diff line number Diff line
@@ -1786,7 +1786,6 @@ static int __init rzg2l_cpg_add_pm_domains(struct rzg2l_cpg_priv *priv) 
		return ret;



	for (unsigned int i = 0; i < info->num_pm_domains; i++) {

		bool always_on = !!(info->pm_domains[i].flags & RZG2L_PD_F_ALWAYS_ON);

		struct rzg2l_cpg_pd *pd;



		pd = devm_kzalloc(dev, sizeof(*pd), GFP_KERNEL);
@@ -1794,8 +1793,7 @@ static int __init rzg2l_cpg_add_pm_domains(struct rzg2l_cpg_priv *priv) 
			return -ENOMEM;



		pd->genpd.name = info->pm_domains[i].name;

		if (always_on)

			pd->genpd.flags = GENPD_FLAG_ALWAYS_ON;

		pd->genpd.flags = info->pm_domains[i].genpd_flags;

		pd->conf = info->pm_domains[i].conf;

		pd->id = info->pm_domains[i].id;

		pd->priv = priv;

drivers/clk/renesas/rzg2l-cpg.h

+3 −7
Original line number Diff line number Diff line
@@ -270,14 +270,14 @@ struct rzg2l_cpg_pm_domain_conf { 
 * struct rzg2l_cpg_pm_domain_init_data - PM domain init data

 * @name: PM domain name

 * @conf: PM domain configuration

 * @flags: RZG2L PM domain flags (see RZG2L_PD_F_*)

 * @genpd_flags: genpd flags (see GENPD_FLAG_*)

 * @id: PM domain ID (similar to the ones defined in

 *      include/dt-bindings/clock/<soc-id>-cpg.h)

 */

struct rzg2l_cpg_pm_domain_init_data {

	const char * const name;

	struct rzg2l_cpg_pm_domain_conf conf;

	u32 flags;

	u32 genpd_flags;

	u16 id;

};
@@ -288,13 +288,9 @@ struct rzg2l_cpg_pm_domain_init_data { 
		.conf = { \

			.mstop = (_mstop_conf), \

		}, \

		.flags = (_flags), \

		.genpd_flags = (_flags), \

	}



/* Power domain flags. */

#define RZG2L_PD_F_ALWAYS_ON	BIT(0)

#define RZG2L_PD_F_NONE		(0)



/**

 * struct rzg2l_cpg_info - SoC-specific CPG Description

 *