Commit dde4b05e authored by Bjorn Helgaas's avatar Bjorn Helgaas
Browse files

Merge branch 'pci/controller/mediatek-gen3' 

- Add optional sys clock ready time setting to avoid sys_clk_rdy signal
  glitching in MT6991 and MT8196 (AngeloGioacchino Del Regno)

- Add DT binding and driver support for MT6991 and MT8196 (AngeloGioacchino
  Del Regno)

* pci/controller/mediatek-gen3:
  PCI: mediatek-gen3: Add support for MediaTek MT8196 SoC
  dt-bindings: PCI: mediatek-gen3: Add support for MT6991/MT8196
  PCI: mediatek-gen3: Implement sys clock ready time setting
parents 836eec3a 81fedb39

Documentation/devicetree/bindings/pci/mediatek-pcie-gen3.yaml

+35 −0
Original line number Diff line number Diff line
@@ -52,7 +52,12 @@ properties: 
              - mediatek,mt8188-pcie

              - mediatek,mt8195-pcie

          - const: mediatek,mt8192-pcie

      - items:

          - enum:

              - mediatek,mt6991-pcie

          - const: mediatek,mt8196-pcie

      - const: mediatek,mt8192-pcie

      - const: mediatek,mt8196-pcie

      - const: airoha,en7581-pcie



  reg:
@@ -212,6 +217,36 @@ allOf: 


        mediatek,pbus-csr: false



  - if:

      properties:

        compatible:

          contains:

            enum:

              - mediatek,mt8196-pcie

    then:

      properties:

        clocks:

          minItems: 6



        clock-names:

          items:

            - const: pl_250m

            - const: tl_26m

            - const: bus

            - const: low_power

            - const: peri_26m

            - const: peri_mem



        resets:

          minItems: 2



        reset-names:

          items:

            - const: phy

            - const: mac



        mediatek,pbus-csr: false



  - if:

      properties:

        compatible:

drivers/pci/controller/pcie-mediatek-gen3.c

+23 −0
Original line number Diff line number Diff line
@@ -102,6 +102,9 @@ 
#define PCIE_MSI_SET_ADDR_HI_BASE	0xc80

#define PCIE_MSI_SET_ADDR_HI_OFFSET	0x04



#define PCIE_RESOURCE_CTRL_REG		0xd2c

#define PCIE_RSRC_SYS_CLK_RDY_TIME_MASK	GENMASK(7, 0)



#define PCIE_ICMD_PM_REG		0x198

#define PCIE_TURN_OFF_LINK		BIT(4)
@@ -149,6 +152,7 @@ enum mtk_gen3_pcie_flags { 
 * struct mtk_gen3_pcie_pdata - differentiate between host generations

 * @power_up: pcie power_up callback

 * @phy_resets: phy reset lines SoC data.

 * @sys_clk_rdy_time_us: System clock ready time override (microseconds)

 * @flags: pcie device flags.

 */

struct mtk_gen3_pcie_pdata {
@@ -157,6 +161,7 @@ struct mtk_gen3_pcie_pdata { 
		const char *id[MAX_NUM_PHY_RESETS];

		int num_resets;

	} phy_resets;

	u8 sys_clk_rdy_time_us;

	u32 flags;

};
@@ -435,6 +440,14 @@ static int mtk_pcie_startup_port(struct mtk_gen3_pcie *pcie) 
		writel_relaxed(val, pcie->base + PCIE_CONF_LINK2_CTL_STS);

	}



	/* If parameter is present, adjust SYS_CLK_RDY_TIME to avoid glitching */

	if (pcie->soc->sys_clk_rdy_time_us) {

		val = readl_relaxed(pcie->base + PCIE_RESOURCE_CTRL_REG);

		FIELD_MODIFY(PCIE_RSRC_SYS_CLK_RDY_TIME_MASK, &val,

			     pcie->soc->sys_clk_rdy_time_us);

		writel_relaxed(val, pcie->base + PCIE_RESOURCE_CTRL_REG);

	}



	/* Set class code */

	val = readl_relaxed(pcie->base + PCIE_PCI_IDS_1);

	val &= ~GENMASK(31, 8);
@@ -1327,6 +1340,15 @@ static const struct mtk_gen3_pcie_pdata mtk_pcie_soc_mt8192 = { 
	},

};



static const struct mtk_gen3_pcie_pdata mtk_pcie_soc_mt8196 = {

	.power_up = mtk_pcie_power_up,

	.phy_resets = {

		.id[0] = "phy",

		.num_resets = 1,

	},

	.sys_clk_rdy_time_us = 10,

};



static const struct mtk_gen3_pcie_pdata mtk_pcie_soc_en7581 = {

	.power_up = mtk_pcie_en7581_power_up,

	.phy_resets = {
@@ -1341,6 +1363,7 @@ static const struct mtk_gen3_pcie_pdata mtk_pcie_soc_en7581 = { 
static const struct of_device_id mtk_pcie_of_match[] = {

	{ .compatible = "airoha,en7581-pcie", .data = &mtk_pcie_soc_en7581 },

	{ .compatible = "mediatek,mt8192-pcie", .data = &mtk_pcie_soc_mt8192 },

	{ .compatible = "mediatek,mt8196-pcie", .data = &mtk_pcie_soc_mt8196 },

	{},

};

MODULE_DEVICE_TABLE(of, mtk_pcie_of_match);