Commit de0c2cdc authored by Johannes Berg's avatar Johannes Berg
Browse files

wifi: iwlwifi: mvm: limit EHT 320 MHz MCS for STEP URM



If the STEP (the interface between MAC and PHY) is in URM
(a lower speed mode) then we cannot use 320 MHz MCS > 9.
Therefore, limit the MCS in our capabilities in this case.
Note that this also limits the TX/rate scaling since that
takes both TX and RX capabilities into account.

Signed-off-by: default avatarJohannes Berg <johannes.berg@intel.com>
Reviewed-by: default avatarGregory Greenman <gregory.greenman@intel.com>
Signed-off-by: default avatarMiri Korenblit <miriam.rachel.korenblit@intel.com>
Link: https://msgid.link/20240123200528.02bae683b7fc.Id5efbb71d45da02c8c4e211d20396637ddd44da8@changeid


Signed-off-by: default avatarJohannes Berg <johannes.berg@intel.com>
parent 84ec2d2e
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+5 −0
Original line number Diff line number Diff line
@@ -1061,6 +1061,11 @@ iwl_nvm_fixup_sband_iftd(struct iwl_trans *trans,
			~IEEE80211_HE_PHY_CAP7_STBC_RX_ABOVE_80MHZ;
	}

	if (trans->step_urm) {
		iftype_data->eht_cap.eht_mcs_nss_supp.bw._320.rx_tx_mcs11_max_nss = 0;
		iftype_data->eht_cap.eht_mcs_nss_supp.bw._320.rx_tx_mcs13_max_nss = 0;
	}

	if (trans->no_160)
		iftype_data->he_cap.he_cap_elem.phy_cap_info[0] &=
			~IEEE80211_HE_PHY_CAP0_CHANNEL_WIDTH_SET_160MHZ_IN_5G;
+3 −0
Original line number Diff line number Diff line
@@ -374,6 +374,9 @@ enum {
#define CNVR_SCU_SD_REGS_SD_REG_ACTIVE_VDIG_MIRROR	0xA29938
#define CNVI_SCU_SEQ_DATA_DW9				0xA27488

#define CNVI_PMU_STEP_FLOW				0xA2D588
#define CNVI_PMU_STEP_FLOW_FORCE_URM			BIT(2)

#define PREG_AUX_BUS_WPROT_0		0xA04CC0

/* device family 9000 WPROT register */
+3 −1
Original line number Diff line number Diff line
@@ -1070,6 +1070,7 @@ struct iwl_trans_txqs {
 * @invalid_tx_cmd: invalid TX command buffer
 * @reduced_cap_sku: reduced capability supported SKU
 * @no_160: device not supporting 160 MHz
 * @step_urm: STEP is in URM, no support for MCS>9 in 320 MHz
 */
struct iwl_trans {
	bool csme_own;
@@ -1093,7 +1094,8 @@ struct iwl_trans {
	char hw_id_str[52];
	u32 sku_id[3];
	bool reduced_cap_sku;
	u8 no_160;
	u8 no_160:1, step_urm:1;

	u8 rx_mpdu_cmd, rx_mpdu_cmd_hdr_size;

	bool pm_support;
+5 −0
Original line number Diff line number Diff line
@@ -677,6 +677,11 @@ static int iwl_run_unified_mvm_ucode(struct iwl_mvm *mvm)
	iwl_dbg_tlv_time_point(&mvm->fwrt, IWL_FW_INI_TIME_POINT_AFTER_ALIVE,
			       NULL);

	if (mvm->trans->trans_cfg->device_family == IWL_DEVICE_FAMILY_BZ)
		mvm->trans->step_urm = !!(iwl_read_umac_prph(mvm->trans,
							     CNVI_PMU_STEP_FLOW) &
						CNVI_PMU_STEP_FLOW_FORCE_URM);

	/* Send init config command to mark that we are sending NVM access
	 * commands
	 */