Commit de0cbc74 authored by Jani Nikula's avatar Jani Nikula
Browse files

drm/i915/irq: remove GEN8_IRQ_RESET_NDX() and GEN8_IRQ_INIT_NDX() macros 



Define register offset triplets for all registers used with
GEN8_IRQ_RESET_NDX() and GEN8_IRQ_INIT_NDX() macros, and call the
underlying gen3_irq_reset() and gen3_irq_init() functions
directly. Remove the macros, along with the macro name concatenation
hackery.

Reviewed-by: default avatarRodrigo Vivi <rodrigo.vivi@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20241002102645.136155-3-jani.nikula@intel.com


Signed-off-by: default avatarJani Nikula <jani.nikula@intel.com>
parent 7a26b3f1

drivers/gpu/drm/i915/display/intel_display_irq.c

+9 −9
Original line number Diff line number Diff line
@@ -1556,7 +1556,7 @@ void gen8_display_irq_reset(struct drm_i915_private *dev_priv) 
	for_each_pipe(dev_priv, pipe)

		if (intel_display_power_is_enabled(dev_priv,

						   POWER_DOMAIN_PIPE(pipe)))

			GEN8_IRQ_RESET_NDX(uncore, DE_PIPE, pipe);

			gen3_irq_reset(uncore, GEN8_DE_PIPE_IRQ_REGS(pipe));



	gen3_irq_reset(uncore, GEN8_DE_PORT_IRQ_REGS);

	gen3_irq_reset(uncore, GEN8_DE_MISC_IRQ_REGS);
@@ -1599,7 +1599,7 @@ void gen11_display_irq_reset(struct drm_i915_private *dev_priv) 
	for_each_pipe(dev_priv, pipe)

		if (intel_display_power_is_enabled(dev_priv,

						   POWER_DOMAIN_PIPE(pipe)))

			GEN8_IRQ_RESET_NDX(uncore, DE_PIPE, pipe);

			gen3_irq_reset(uncore, GEN8_DE_PIPE_IRQ_REGS(pipe));



	gen3_irq_reset(uncore, GEN8_DE_PORT_IRQ_REGS);

	gen3_irq_reset(uncore, GEN8_DE_MISC_IRQ_REGS);
@@ -1630,7 +1630,7 @@ void gen8_irq_power_well_post_enable(struct drm_i915_private *dev_priv, 
	}



	for_each_pipe_masked(dev_priv, pipe, pipe_mask)

		GEN8_IRQ_INIT_NDX(uncore, DE_PIPE, pipe,

		gen3_irq_init(uncore, GEN8_DE_PIPE_IRQ_REGS(pipe),

			      dev_priv->display.irq.de_irq_mask[pipe],

			      ~dev_priv->display.irq.de_irq_mask[pipe] | extra_ier);
@@ -1651,7 +1651,7 @@ void gen8_irq_power_well_pre_disable(struct drm_i915_private *dev_priv, 
	}



	for_each_pipe_masked(dev_priv, pipe, pipe_mask)

		GEN8_IRQ_RESET_NDX(uncore, DE_PIPE, pipe);

		gen3_irq_reset(uncore, GEN8_DE_PIPE_IRQ_REGS(pipe));



	spin_unlock_irq(&dev_priv->irq_lock);
@@ -1839,7 +1839,7 @@ void gen8_de_irq_postinstall(struct drm_i915_private *dev_priv) 


		if (intel_display_power_is_enabled(dev_priv,

						   POWER_DOMAIN_PIPE(pipe)))

			GEN8_IRQ_INIT_NDX(uncore, DE_PIPE, pipe,

			gen3_irq_init(uncore, GEN8_DE_PIPE_IRQ_REGS(pipe),

				      dev_priv->display.irq.de_irq_mask[pipe],

				      de_pipe_enables);

	}

drivers/gpu/drm/i915/gt/intel_gt_irq.c

+8 −8
Original line number Diff line number Diff line
@@ -452,10 +452,10 @@ void gen8_gt_irq_reset(struct intel_gt *gt) 
{

	struct intel_uncore *uncore = gt->uncore;



	GEN8_IRQ_RESET_NDX(uncore, GT, 0);

	GEN8_IRQ_RESET_NDX(uncore, GT, 1);

	GEN8_IRQ_RESET_NDX(uncore, GT, 2);

	GEN8_IRQ_RESET_NDX(uncore, GT, 3);

	gen3_irq_reset(uncore, GEN8_GT_IRQ_REGS(0));

	gen3_irq_reset(uncore, GEN8_GT_IRQ_REGS(1));

	gen3_irq_reset(uncore, GEN8_GT_IRQ_REGS(2));

	gen3_irq_reset(uncore, GEN8_GT_IRQ_REGS(3));

}



void gen8_gt_irq_postinstall(struct intel_gt *gt)
@@ -476,14 +476,14 @@ void gen8_gt_irq_postinstall(struct intel_gt *gt) 


	gt->pm_ier = 0x0;

	gt->pm_imr = ~gt->pm_ier;

	GEN8_IRQ_INIT_NDX(uncore, GT, 0, ~gt_interrupts[0], gt_interrupts[0]);

	GEN8_IRQ_INIT_NDX(uncore, GT, 1, ~gt_interrupts[1], gt_interrupts[1]);

	gen3_irq_init(uncore, GEN8_GT_IRQ_REGS(0), ~gt_interrupts[0], gt_interrupts[0]);

	gen3_irq_init(uncore, GEN8_GT_IRQ_REGS(1), ~gt_interrupts[1], gt_interrupts[1]);

	/*

	 * RPS interrupts will get enabled/disabled on demand when RPS itself

	 * is enabled/disabled. Same wil be the case for GuC interrupts.

	 */

	GEN8_IRQ_INIT_NDX(uncore, GT, 2, gt->pm_imr, gt->pm_ier);

	GEN8_IRQ_INIT_NDX(uncore, GT, 3, ~gt_interrupts[3], gt_interrupts[3]);

	gen3_irq_init(uncore, GEN8_GT_IRQ_REGS(2), gt->pm_imr, gt->pm_ier);

	gen3_irq_init(uncore, GEN8_GT_IRQ_REGS(3), ~gt_interrupts[3], gt_interrupts[3]);

}



static void gen5_gt_update_irq(struct intel_gt *gt,

drivers/gpu/drm/i915/i915_irq.h

+0 −17
Original line number Diff line number Diff line
@@ -47,21 +47,4 @@ void gen3_irq_reset(struct intel_uncore *uncore, struct i915_irq_regs regs); 
void gen3_irq_init(struct intel_uncore *uncore, struct i915_irq_regs regs,

		   u32 imr_val, u32 ier_val);



#define GEN8_IRQ_RESET_NDX(uncore, type, which) \

({ \

	unsigned int which_ = which; \

	gen3_irq_reset((uncore), I915_IRQ_REGS(GEN8_##type##_IMR(which_), \

					       GEN8_##type##_IER(which_), \

					       GEN8_##type##_IIR(which_))); \

})



#define GEN8_IRQ_INIT_NDX(uncore, type, which, imr_val, ier_val) \

({ \

	unsigned int which_ = which; \

	gen3_irq_init((uncore), I915_IRQ_REGS(GEN8_##type##_IMR(which_), \

					      GEN8_##type##_IER(which_), \

					      GEN8_##type##_IIR(which_)), \

		      imr_val, ier_val); \

})



#endif /* __I915_IRQ_H__ */

drivers/gpu/drm/i915/i915_reg.h

+8 −0
Original line number Diff line number Diff line
@@ -2491,6 +2491,10 @@ 
#define GEN8_GT_IIR(which) _MMIO(0x44308 + (0x10 * (which)))

#define GEN8_GT_IER(which) _MMIO(0x4430c + (0x10 * (which)))



#define GEN8_GT_IRQ_REGS(which)		I915_IRQ_REGS(GEN8_GT_IMR(which), \

						      GEN8_GT_IER(which), \

						      GEN8_GT_IIR(which))



#define GEN8_RCS_IRQ_SHIFT 0

#define GEN8_BCS_IRQ_SHIFT 16

#define GEN8_VCS0_IRQ_SHIFT 0  /* NB: VCS1 in bspec! */
@@ -2542,6 +2546,10 @@ 
#define  GEN8_PIPE_VSYNC		REG_BIT(1)

#define  GEN8_PIPE_VBLANK		REG_BIT(0)



#define GEN8_DE_PIPE_IRQ_REGS(pipe)	I915_IRQ_REGS(GEN8_DE_PIPE_IMR(pipe), \

						      GEN8_DE_PIPE_IER(pipe), \

						      GEN8_DE_PIPE_IIR(pipe))



#define _HPD_PIN_DDI(hpd_pin)	((hpd_pin) - HPD_PORT_A)

#define _HPD_PIN_TC(hpd_pin)	((hpd_pin) - HPD_PORT_TC1)