Commit de20037e authored by Breno Leitao's avatar Breno Leitao Committed by Peter Zijlstra
Browse files

perf/x86/amd: Warn only on new bits set 



Warning at every leaking bits can cause a flood of message, triggering
various stall-warning mechanisms to fire, including CSD locks, which
makes the machine to be unusable.

Track the bits that are being leaked, and only warn when a new bit is
set.

That said, this patch will help with the following issues:

1) It will tell us which bits are being set, so, it is easy to
   communicate it back to vendor, and to do a root-cause analyzes.

2) It avoid the machine to be unusable, because, worst case
   scenario, the user gets less than 60 WARNs (one per unhandled bit).

Suggested-by: default avatarPaul E. McKenney <paulmck@kernel.org>
Signed-off-by: default avatarBreno Leitao <leitao@debian.org>
Signed-off-by: default avatarPeter Zijlstra (Intel) <peterz@infradead.org>
Reviewed-by: default avatarSandipan Das <sandipan.das@amd.com>
Reviewed-by: default avatarPaul E. McKenney <paulmck@kernel.org>
Link: https://lkml.kernel.org/r/20241001141020.2620361-1-leitao@debian.org
parent 6c74ca7a

arch/x86/events/amd/core.c

+8 −2
Original line number Diff line number Diff line
@@ -943,11 +943,12 @@ static int amd_pmu_v2_snapshot_branch_stack(struct perf_branch_entry *entries, u 
static int amd_pmu_v2_handle_irq(struct pt_regs *regs)

{

	struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);

	static atomic64_t status_warned = ATOMIC64_INIT(0);

	u64 reserved, status, mask, new_bits, prev_bits;

	struct perf_sample_data data;

	struct hw_perf_event *hwc;

	struct perf_event *event;

	int handled = 0, idx;

	u64 reserved, status, mask;

	bool pmu_enabled;



	/*
@@ -1012,7 +1013,12 @@ static int amd_pmu_v2_handle_irq(struct pt_regs *regs) 
	 * the corresponding PMCs are expected to be inactive according to the

	 * active_mask

	 */

	WARN_ON(status > 0);

	if (status > 0) {

		prev_bits = atomic64_fetch_or(status, &status_warned);

		// A new bit was set for the very first time.

		new_bits = status & ~prev_bits;

		WARN(new_bits, "New overflows for inactive PMCs: %llx\n", new_bits);

	}



	/* Clear overflow and freeze bits */

	amd_pmu_ack_global_status(~status);