Commit de796fc1 authored by Pali Rohár's avatar Pali Rohár Committed by Thomas Gleixner
Browse files

irqchip/armada-370-xp: Only call ipi_resume() if IPI is available



IPI is available only on systems where the mpic controller does not have a
parent interrupt defined (e.g. on Armada XP). If a parent interrupt is
defined, inter-processor interrupts are handled by an interrupt controller
higher in the hierarchy (most probably a parent GIC).

Only call ipi_resume() on systems where IPI is available in the mpic
controller.

Signed-off-by: default avatarPali Rohár <pali@kernel.org>
Signed-off-by: default avatarMarek Behún <kabel@kernel.org>
Signed-off-by: default avatarThomas Gleixner <tglx@linutronix.de>
Reviewed-by: default avatarAndrew Lunn <andrew@lunn.ch>

[ refactored a little and changed commit message ]
parent 3cef7382
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+16 −2
Original line number Diff line number Diff line
@@ -29,6 +29,7 @@
#include <linux/slab.h>
#include <linux/syscore_ops.h>
#include <linux/msi.h>
#include <linux/types.h>
#include <asm/mach/arch.h>
#include <asm/exception.h>
#include <asm/smp_plat.h>
@@ -156,6 +157,17 @@ static DEFINE_MUTEX(msi_used_lock);
static phys_addr_t msi_doorbell_addr;
#endif

static inline bool is_ipi_available(void)
{
	/*
	 * We distinguish IPI availability in the IC by the IC not having a
	 * parent irq defined. If a parent irq is defined, there is a parent
	 * interrupt controller (e.g. GIC) that takes care of inter-processor
	 * interrupts.
	 */
	return parent_irq <= 0;
}

static inline bool is_percpu_irq(irq_hw_number_t irq)
{
	if (irq <= ARMADA_370_XP_MAX_PER_CPU_IRQS)
@@ -521,6 +533,7 @@ static void armada_xp_mpic_reenable_percpu(void)
		armada_370_xp_irq_unmask(data);
	}

	if (is_ipi_available())
		ipi_resume();

	armada_370_xp_msi_reenable_percpu();
@@ -744,6 +757,7 @@ static void armada_370_xp_mpic_resume(void)
	if (doorbell_mask_reg & PCI_MSI_DOORBELL_MASK)
		writel(1, per_cpu_int_base + ARMADA_370_XP_INT_CLEAR_MASK_OFFS);

	if (is_ipi_available())
		ipi_resume();
}