Commit deb76992 authored by Ravi Kumar Vodapalli's avatar Ravi Kumar Vodapalli Committed by Gustavo Sousa
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drm/i915/xe3p_lpd: Adapt to updates on MBUS_CTL/DBUF_CTL registers 



Xe3p_LPD updated fields of registers MBUS_CTL and DBUF_CTL to
accommodate for higher MDCLK:CDCLK ratios.  Update the code to use the
new fields.

The field MBUS_TRANSLATION_THROTTLE_MIN_MASK was changed from range
[15:13] to [16:13].  Since bit 16 is not reserved in previous display
IPs and already used for something else, we can't simply extend the mask
definition to include it, but rather define an Xe3p-specific mask and
select the correct one to use based on the IP version.

Similarly, DBUF_MIN_TRACKER_STATE_SERVICE_MASK was changed from range
[18:16] to [20:16]. For the same reasons stated above, it needs a
Xe3p-specific mask definition.

v2:
  - Keep definitions in the same line (i.e. without line continuation
    breaks) for better readability. (Jani)
v3:
  - Keep mask fields sorted by the upper limit. (Matt)
  - Extend commit message to indicate why we need Xe3p-specific
    definitions of the masks instead of just extending the existing
    ones. (Matt)

Bspec: 68868, 68872
Cc: Jani Nikula <jani.nikula@linux.intel.com>
Signed-off-by: default avatarRavi Kumar Vodapalli <ravi.kumar.vodapalli@intel.com>
Reviewed-by: default avatarMatt Roper <matthew.d.roper@intel.com>
Link: https://patch.msgid.link/20251103-xe3p_lpd-basic-enabling-v3-18-00e87b510ae7@intel.com


Signed-off-by: default avatarGustavo Sousa <gustavo.sousa@intel.com>
parent e2a06cf8

drivers/gpu/drm/i915/display/skl_watermark.c

+12 −4
Original line number Diff line number Diff line
@@ -3486,7 +3486,10 @@ void intel_dbuf_mdclk_cdclk_ratio_update(struct intel_display *display, 
	if (!HAS_MBUS_JOINING(display))

		return;



	if (DISPLAY_VER(display) >= 20)

	if (DISPLAY_VER(display) >= 35)

		intel_de_rmw(display, MBUS_CTL, XE3P_MBUS_TRANSLATION_THROTTLE_MIN_MASK,

			     XE3P_MBUS_TRANSLATION_THROTTLE_MIN(ratio - 1));

	else if (DISPLAY_VER(display) >= 20)

		intel_de_rmw(display, MBUS_CTL, MBUS_TRANSLATION_THROTTLE_MIN_MASK,

			     MBUS_TRANSLATION_THROTTLE_MIN(ratio - 1));
@@ -3497,6 +3500,11 @@ void intel_dbuf_mdclk_cdclk_ratio_update(struct intel_display *display, 
		    ratio, str_yes_no(joined_mbus));



	for_each_dbuf_slice(display, slice)

		if (DISPLAY_VER(display) >= 35)

			intel_de_rmw(display, DBUF_CTL_S(slice),

				     XE3P_DBUF_MIN_TRACKER_STATE_SERVICE_MASK,

				     XE3P_DBUF_MIN_TRACKER_STATE_SERVICE(ratio - 1));

		else

			intel_de_rmw(display, DBUF_CTL_S(slice),

				     DBUF_MIN_TRACKER_STATE_SERVICE_MASK,

				     DBUF_MIN_TRACKER_STATE_SERVICE(ratio - 1));

drivers/gpu/drm/i915/display/skl_watermark_regs.h

+28 −24
Original line number Diff line number Diff line
@@ -40,6 +40,8 @@ 
#define   MBUS_JOIN_PIPE_SELECT_MASK			REG_GENMASK(28, 26)

#define   MBUS_JOIN_PIPE_SELECT(pipe)			REG_FIELD_PREP(MBUS_JOIN_PIPE_SELECT_MASK, pipe)

#define   MBUS_JOIN_PIPE_SELECT_NONE			MBUS_JOIN_PIPE_SELECT(7)

#define   XE3P_MBUS_TRANSLATION_THROTTLE_MIN_MASK	REG_GENMASK(16, 13)

#define   XE3P_MBUS_TRANSLATION_THROTTLE_MIN(val)	REG_FIELD_PREP(XE3P_MBUS_TRANSLATION_THROTTLE_MIN_MASK, val)

#define   MBUS_TRANSLATION_THROTTLE_MIN_MASK		REG_GENMASK(15, 13)

#define   MBUS_TRANSLATION_THROTTLE_MIN(val)		REG_FIELD_PREP(MBUS_TRANSLATION_THROTTLE_MIN_MASK, val)
@@ -64,6 +66,8 @@ 
#define  DBUF_POWER_STATE				REG_BIT(30)

#define  DBUF_TRACKER_STATE_SERVICE_MASK		REG_GENMASK(23, 19)

#define  DBUF_TRACKER_STATE_SERVICE(x)			REG_FIELD_PREP(DBUF_TRACKER_STATE_SERVICE_MASK, x)

#define  XE3P_DBUF_MIN_TRACKER_STATE_SERVICE_MASK	REG_GENMASK(20, 16)

#define  XE3P_DBUF_MIN_TRACKER_STATE_SERVICE(x)		REG_FIELD_PREP(XE3P_DBUF_MIN_TRACKER_STATE_SERVICE_MASK, x)

#define  DBUF_MIN_TRACKER_STATE_SERVICE_MASK		REG_GENMASK(18, 16) /* ADL-P+ */

#define  DBUF_MIN_TRACKER_STATE_SERVICE(x)		REG_FIELD_PREP(DBUF_MIN_TRACKER_STATE_SERVICE_MASK, x) /* ADL-P+ */