Unverified Commit dedf9c93 authored by Larisa Grigore's avatar Larisa Grigore Committed by Mark Brown
Browse files

spi: spi-fsl-lpspi: Clear status register after disabling the module 



Clear the error flags after disabling the module to avoid the case when
a flag is set again between flag clear and module disable. And use
SR_CLEAR_MASK to replace hardcoded value for improved readability.

Although fsl_lpspi_reset() was only introduced in commit a15dc3d6
("spi: lpspi: Fix CLK pin becomes low before one transfer"), the
original driver only reset SR in the interrupt handler, making it
vulnerable to the same issue. Therefore the fixes commit is set at the
introduction of the driver.

Fixes: 5314987d ("spi: imx: add lpspi bus driver")
Signed-off-by: default avatarLarisa Grigore <larisa.grigore@nxp.com>
Signed-off-by: default avatarCiprian Marian Costea <ciprianmarian.costea@nxp.com>
Reviewed-by: default avatarFrank Li <Frank.Li@nxp.com>
Signed-off-by: default avatarJames Clark <james.clark@linaro.org>
Link: https://patch.msgid.link/20250828-james-nxp-lpspi-v2-4-6262b9aa9be4@linaro.org


Signed-off-by: default avatarMark Brown <broonie@kernel.org>
parent e811b088

drivers/spi/spi-fsl-lpspi.c

+5 −4
Original line number Diff line number Diff line
@@ -83,6 +83,8 @@ 
#define TCR_RXMSK	BIT(19)

#define TCR_TXMSK	BIT(18)



#define SR_CLEAR_MASK	GENMASK(13, 8)



struct fsl_lpspi_devtype_data {

	u8 prescale_max;

};
@@ -535,14 +537,13 @@ static int fsl_lpspi_reset(struct fsl_lpspi_data *fsl_lpspi) 
		fsl_lpspi_intctrl(fsl_lpspi, 0);

	}



	/* W1C for all flags in SR */

	temp = 0x3F << 8;

	writel(temp, fsl_lpspi->base + IMX7ULP_SR);



	/* Clear FIFO and disable module */

	temp = CR_RRF | CR_RTF;

	writel(temp, fsl_lpspi->base + IMX7ULP_CR);



	/* W1C for all flags in SR */

	writel(SR_CLEAR_MASK, fsl_lpspi->base + IMX7ULP_SR);



	return 0;

}