Commit def3f83e authored by Austin Zheng's avatar Austin Zheng Committed by Alex Deucher
Browse files

drm/amd/display: DML21 Reintegration 



Update logging macros for detailed debugging
Update structs to contain more detailed information
Add HDMI 16 and 20 Gbps rates

Reviewed-by: default avatarAlvin Lee <alvin.lee2@amd.com>
Signed-off-by: default avatarAustin Zheng <Austin.Zheng@amd.com>
Signed-off-by: default avatarFangzhi Zuo <jerry.zuo@amd.com>
Tested-by: default avatarDaniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent f8fa4dfb

drivers/gpu/drm/amd/display/dc/dml2/dml21/inc/dml_top_dchub_registers.h

+1 −0
Original line number Diff line number Diff line
@@ -46,6 +46,7 @@ struct dml2_display_dlg_regs { 
	uint32_t dst_y_delta_drq_limit;

	uint32_t refcyc_per_vm_dmdata;

	uint32_t dmdata_dl_delta;

	uint32_t dst_y_svp_drq_limit;



	// MRQ

	uint32_t refcyc_per_meta_chunk_vblank_l;

drivers/gpu/drm/amd/display/dc/dml2/dml21/inc/dml_top_display_cfg_types.h

+2 −0
Original line number Diff line number Diff line
@@ -222,6 +222,7 @@ struct dml2_composition_cfg { 


	struct {

		bool enabled;

		bool upsp_enabled;

		struct {

			double h_ratio;

			double v_ratio;
@@ -426,6 +427,7 @@ struct dml2_stream_parameters { 


struct dml2_display_cfg {

	bool gpuvm_enable;

	bool ffbm_enable;

	bool hostvm_enable;



	// Allocate DET proportionally between streams based on pixel rate

drivers/gpu/drm/amd/display/dc/dml2/dml21/inc/dml_top_soc_parameter_types.h

+1 −0
Original line number Diff line number Diff line
@@ -93,6 +93,7 @@ struct dml2_soc_power_management_parameters { 
	double dram_clk_change_write_only_us;

	double fclk_change_blackout_us;

	double g7_ppt_blackout_us;

	double g7_temperature_read_blackout_us;

	double stutter_enter_plus_exit_latency_us;

	double stutter_exit_latency_us;

	double z8_stutter_enter_plus_exit_latency_us;

drivers/gpu/drm/amd/display/dc/dml2/dml21/inc/dml_top_types.h

+3 −1
Original line number Diff line number Diff line
@@ -53,7 +53,9 @@ enum dml2_output_type_and_rate__rate { 
	dml2_output_rate_hdmi_rate_6x4 = 9,

	dml2_output_rate_hdmi_rate_8x4 = 10,

	dml2_output_rate_hdmi_rate_10x4 = 11,

	dml2_output_rate_hdmi_rate_12x4 = 12

	dml2_output_rate_hdmi_rate_12x4 = 12,

	dml2_output_rate_hdmi_rate_16x4 = 13,

	dml2_output_rate_hdmi_rate_20x4 = 14

};



struct dml2_pmo_options {

drivers/gpu/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

+4 −0
Original line number Diff line number Diff line
@@ -13069,6 +13069,10 @@ void dml2_core_calcs_get_informative(const struct dml2_core_internal_display_mod 
			out->informative.mode_support_info.OutputRate[k] = dml2_output_rate_hdmi_rate_10x4;

		else if (mode_lib->ms.support.OutputRate[k] == dml2_core_internal_output_rate_hdmi_rate_12x4)

			out->informative.mode_support_info.OutputRate[k] = dml2_output_rate_hdmi_rate_12x4;

		else if (mode_lib->ms.support.OutputRate[k] == dml2_core_internal_output_rate_hdmi_rate_16x4)

			out->informative.mode_support_info.OutputRate[k] = dml2_output_rate_hdmi_rate_16x4;

		else if (mode_lib->ms.support.OutputRate[k] == dml2_core_internal_output_rate_hdmi_rate_20x4)

			out->informative.mode_support_info.OutputRate[k] = dml2_output_rate_hdmi_rate_20x4;









		out->informative.mode_support_info.AlignedYPitch[k] = mode_lib->ms.support.AlignedYPitch[k];









		out->informative.mode_support_info.AlignedCPitch[k] = mode_lib->ms.support.AlignedCPitch[k];