Commit df3f3c56 authored by Karol Kolacinski's avatar Karol Kolacinski Committed by Tony Nguyen
Browse files

ice: wait before enabling TSPLL 



To ensure proper operation, wait for 10 to 20 microseconds before
enabling TSPLL.

Adjust wait time after enabling TSPLL from 1-5 ms to 1-2 ms.

Those values are empirical and tested on multiple HW configurations.

Reviewed-by: default avatarMilena Olech <milena.olech@intel.com>
Signed-off-by: default avatarKarol Kolacinski <karol.kolacinski@intel.com>
Signed-off-by: default avatarTony Nguyen <anthony.l.nguyen@intel.com>
parent 5755b4c0

drivers/net/ethernet/intel/ice/ice_tspll.c

+10 −4
Original line number Diff line number Diff line
@@ -261,6 +261,9 @@ static int ice_tspll_cfg_e82x(struct ice_hw *hw, enum ice_tspll_freq clk_freq, 
	if (err)

		return err;



	/* Wait to ensure everything is stable */

	usleep_range(10, 20);



	/* Finally, enable the PLL */

	r24 |= ICE_CGU_R23_R24_TSPLL_ENABLE;
@@ -268,8 +271,8 @@ static int ice_tspll_cfg_e82x(struct ice_hw *hw, enum ice_tspll_freq clk_freq, 
	if (err)

		return err;



	/* Wait to verify if the PLL locks */

	usleep_range(1000, 5000);

	/* Wait at least 1 ms to verify if the PLL locks */

	usleep_range(USEC_PER_MSEC, 2 * USEC_PER_MSEC);



	err = ice_read_cgu_reg(hw, ICE_CGU_RO_BWM_LF, &val);

	if (err)
@@ -445,6 +448,9 @@ static int ice_tspll_cfg_e825c(struct ice_hw *hw, enum ice_tspll_freq clk_freq, 
	if (err)

		return err;



	/* Wait to ensure everything is stable */

	usleep_range(10, 20);



	/* Finally, enable the PLL */

	r23 |= ICE_CGU_R23_R24_TSPLL_ENABLE;
@@ -452,8 +458,8 @@ static int ice_tspll_cfg_e825c(struct ice_hw *hw, enum ice_tspll_freq clk_freq, 
	if (err)

		return err;



	/* Wait to verify if the PLL locks */

	usleep_range(1000, 5000);

	/* Wait at least 1 ms to verify if the PLL locks */

	usleep_range(USEC_PER_MSEC, 2 * USEC_PER_MSEC);



	err = ice_read_cgu_reg(hw, ICE_CGU_RO_LOCK, &val);

	if (err)