Commit df3fb27a authored by Noralf Trønnes's avatar Noralf Trønnes
Browse files

drm/mipi-dbi: Make bits per word configurable for pixel transfers 



MIPI DCS write/set commands have 8 bit parameters except for the
write_memory commands where it depends on the pixel format.
drm_mipi_dbi does currently only support RGB565 which is 16-bit and it
has to make sure that the pixels enters the SPI bus in big endian format
since the MIPI DBI spec doesn't have support for little endian.

drm_mipi_dbi is optimized for DBI interface option 3 which means that the
16-bit bytes are swapped by the upper layer if the SPI bus does not
support 16 bits per word, signified by the swap_bytes member.

In order to support both 16-bit and 24-bit pixel transfers we need a way
to tell the DBI command layer the format of the buffer. Add a
write_memory_bpw member that the upper layer can use to tell how many
bits per word to use for the SPI transfer.

v4:
- Expand the commit message (Dmitry)

Reviewed-by: default avatarDmitry Baryshkov <dmitry.baryshkov@linaro.org>
Link: https://patchwork.freedesktop.org/patch/msgid/20240604-panel-mipi-dbi-rgb666-v4-3-d7c2bcb9b78d@tronnes.org


Signed-off-by: default avatarNoralf Trønnes <noralf@tronnes.org>
parent f34f014c

drivers/gpu/drm/drm_mipi_dbi.c

+10 −4
Original line number Diff line number Diff line
@@ -1079,7 +1079,7 @@ static int mipi_dbi_typec1_command_read(struct mipi_dbi *dbi, u8 *cmd, 
static int mipi_dbi_typec1_command(struct mipi_dbi *dbi, u8 *cmd,

				   u8 *parameters, size_t num)

{

	unsigned int bpw = (*cmd == MIPI_DCS_WRITE_MEMORY_START) ? 16 : 8;

	unsigned int bpw = 8;

	int ret;



	if (mipi_dbi_command_is_read(dbi, *cmd))
@@ -1091,6 +1091,9 @@ static int mipi_dbi_typec1_command(struct mipi_dbi *dbi, u8 *cmd, 
	if (ret || !num)

		return ret;



	if (*cmd == MIPI_DCS_WRITE_MEMORY_START)

		bpw = dbi->write_memory_bpw;



	return mipi_dbi_spi1_transfer(dbi, 1, parameters, num, bpw);

}
@@ -1184,8 +1187,8 @@ static int mipi_dbi_typec3_command(struct mipi_dbi *dbi, u8 *cmd, 
	if (ret || !num)

		return ret;



	if (*cmd == MIPI_DCS_WRITE_MEMORY_START && !dbi->swap_bytes)

		bpw = 16;

	if (*cmd == MIPI_DCS_WRITE_MEMORY_START)

		bpw = dbi->write_memory_bpw;



	spi_bus_lock(spi->controller);

	gpiod_set_value_cansleep(dbi->dc, 1);
@@ -1256,12 +1259,15 @@ int mipi_dbi_spi_init(struct spi_device *spi, struct mipi_dbi *dbi, 


	dbi->spi = spi;

	dbi->read_commands = mipi_dbi_dcs_read_commands;

	dbi->write_memory_bpw = 16;



	if (dc) {

		dbi->command = mipi_dbi_typec3_command;

		dbi->dc = dc;

		if (!spi_is_bpw_supported(spi, 16))

		if (!spi_is_bpw_supported(spi, 16)) {

			dbi->write_memory_bpw = 8;

			dbi->swap_bytes = true;

		}

	} else {

		dbi->command = mipi_dbi_typec1_command;

		dbi->tx_buf9_len = SZ_16K;

include/drm/drm_mipi_dbi.h

+5 −0
Original line number Diff line number Diff line
@@ -56,6 +56,11 @@ struct mipi_dbi { 
	 */

	struct spi_device *spi;



	/**

	 * @write_memory_bpw: Bits per word used on a MIPI_DCS_WRITE_MEMORY_START transfer

	 */

	unsigned int write_memory_bpw;



	/**

	 * @dc: Optional D/C gpio.

	 */