Unverified Commit df513ed4 authored by Heiko Stuebner's avatar Heiko Stuebner Committed by Palmer Dabbelt
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RISC-V: add helper function to read the vector VLEN 



VLEN describes the length of each vector register and some instructions
need specific minimal VLENs to work correctly.

The vector code already includes a variable riscv_v_vsize that contains
the value of "32 vector registers with vlenb length" that gets filled
during boot. vlenb is the value contained in the CSR_VLENB register and
the value represents "VLEN / 8".

So add riscv_vector_vlen() to return the actual VLEN value for in-kernel
users when they need to check the available VLEN.

Signed-off-by: default avatarHeiko Stuebner <heiko.stuebner@vrull.eu>
Reviewed-by: default avatarEric Biggers <ebiggers@google.com>
Signed-off-by: default avatarJerry Shih <jerry.shih@sifive.com>
Signed-off-by: default avatarEric Biggers <ebiggers@google.com>
Link: https://lore.kernel.org/r/20240122002024.27477-2-ebiggers@kernel.org


Signed-off-by: default avatarPalmer Dabbelt <palmer@rivosinc.com>
parent 6613476e

arch/riscv/include/asm/vector.h

+11 −0
Original line number Diff line number Diff line
@@ -284,4 +284,15 @@ static inline bool riscv_v_vstate_ctrl_user_allowed(void) { return false; } 


#endif /* CONFIG_RISCV_ISA_V */



/*

 * Return the implementation's vlen value.

 *

 * riscv_v_vsize contains the value of "32 vector registers with vlenb length"

 * so rebuild the vlen value in bits from it.

 */

static inline int riscv_vector_vlen(void)

{

	return riscv_v_vsize / 32 * 8;

}



#endif /* ! __ASM_RISCV_VECTOR_H */