Commit df71879b authored by Dmitry Baryshkov's avatar Dmitry Baryshkov Committed by Vinod Koul
Browse files

phy: qcom: sgmii-eth: use existing register definitions 



The Qualcomm SGMII SerDes PHY is a QMP PHY. As such, it uses standard
registers for QSERDES COM/RX/TX regions. Use register defines from the
existing headers.

Cc: Bartosz Golaszewski <bartosz.golaszewski@linaro.org>
Signed-off-by: default avatarDmitry Baryshkov <dmitry.baryshkov@linaro.org>
Link: https://lore.kernel.org/r/20240126-phy-qmp-merge-common-v2-7-a463d0b57836@linaro.org


Signed-off-by: default avatarVinod Koul <vkoul@kernel.org>
parent fe3ec760

drivers/phy/qualcomm/phy-qcom-sgmii-eth.c

+149 −218
Original line number Diff line number Diff line
@@ -11,83 +11,14 @@ 
#include <linux/platform_device.h>

#include <linux/regmap.h>



#define QSERDES_QMP_PLL					0x0

#define QSERDES_COM_BIN_VCOCAL_CMP_CODE1_MODE0		(QSERDES_QMP_PLL + 0x1ac)

#define QSERDES_COM_BIN_VCOCAL_CMP_CODE2_MODE0		(QSERDES_QMP_PLL + 0x1b0)

#define QSERDES_COM_BIN_VCOCAL_HSCLK_SEL		(QSERDES_QMP_PLL + 0x1bc)

#define QSERDES_COM_CORE_CLK_EN				(QSERDES_QMP_PLL + 0x174)

#define QSERDES_COM_CORECLK_DIV_MODE0			(QSERDES_QMP_PLL + 0x168)

#define QSERDES_COM_CP_CTRL_MODE0			(QSERDES_QMP_PLL + 0x74)

#define QSERDES_COM_DEC_START_MODE0			(QSERDES_QMP_PLL + 0xbc)

#define QSERDES_COM_DIV_FRAC_START1_MODE0		(QSERDES_QMP_PLL + 0xcc)

#define QSERDES_COM_DIV_FRAC_START2_MODE0		(QSERDES_QMP_PLL + 0xd0)

#define QSERDES_COM_DIV_FRAC_START3_MODE0		(QSERDES_QMP_PLL + 0xd4)

#define QSERDES_COM_HSCLK_HS_SWITCH_SEL			(QSERDES_QMP_PLL + 0x15c)

#define QSERDES_COM_HSCLK_SEL				(QSERDES_QMP_PLL + 0x158)

#define QSERDES_COM_LOCK_CMP1_MODE0			(QSERDES_QMP_PLL + 0xac)

#define QSERDES_COM_LOCK_CMP2_MODE0			(QSERDES_QMP_PLL + 0xb0)

#define QSERDES_COM_PLL_CCTRL_MODE0			(QSERDES_QMP_PLL + 0x84)

#define QSERDES_COM_PLL_IVCO				(QSERDES_QMP_PLL + 0x58)

#define QSERDES_COM_PLL_RCTRL_MODE0			(QSERDES_QMP_PLL + 0x7c)

#define QSERDES_COM_SYSCLK_EN_SEL			(QSERDES_QMP_PLL + 0x94)

#define QSERDES_COM_VCO_TUNE1_MODE0			(QSERDES_QMP_PLL + 0x110)

#define QSERDES_COM_VCO_TUNE2_MODE0			(QSERDES_QMP_PLL + 0x114)

#define QSERDES_COM_VCO_TUNE_INITVAL2			(QSERDES_QMP_PLL + 0x124)

#define QSERDES_COM_C_READY_STATUS			(QSERDES_QMP_PLL + 0x178)

#define QSERDES_COM_CMN_STATUS				(QSERDES_QMP_PLL + 0x140)

#include "phy-qcom-qmp-qserdes-com-v5.h"

#include "phy-qcom-qmp-qserdes-txrx-v5.h"



#define QSERDES_QMP_PLL					0x0

#define QSERDES_RX					0x600

#define QSERDES_RX_UCDR_FO_GAIN				(QSERDES_RX + 0x8)

#define QSERDES_RX_UCDR_SO_GAIN				(QSERDES_RX + 0x14)

#define QSERDES_RX_UCDR_FASTLOCK_FO_GAIN		(QSERDES_RX + 0x30)

#define QSERDES_RX_UCDR_SO_SATURATION_AND_ENABLE	(QSERDES_RX + 0x34)

#define QSERDES_RX_UCDR_FASTLOCK_COUNT_LOW		(QSERDES_RX + 0x3c)

#define QSERDES_RX_UCDR_FASTLOCK_COUNT_HIGH		(QSERDES_RX + 0x40)

#define QSERDES_RX_UCDR_PI_CONTROLS			(QSERDES_RX + 0x44)

#define QSERDES_RX_UCDR_PI_CTRL2			(QSERDES_RX + 0x48)

#define QSERDES_RX_RX_TERM_BW				(QSERDES_RX + 0x80)

#define QSERDES_RX_VGA_CAL_CNTRL2			(QSERDES_RX + 0xd8)

#define QSERDES_RX_GM_CAL				(QSERDES_RX + 0xdc)

#define QSERDES_RX_RX_EQU_ADAPTOR_CNTRL1		(QSERDES_RX + 0xe8)

#define QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2		(QSERDES_RX + 0xec)

#define QSERDES_RX_RX_EQU_ADAPTOR_CNTRL3		(QSERDES_RX + 0xf0)

#define QSERDES_RX_RX_EQU_ADAPTOR_CNTRL4		(QSERDES_RX + 0xf4)

#define QSERDES_RX_RX_IDAC_TSETTLE_LOW			(QSERDES_RX + 0xf8)

#define QSERDES_RX_RX_IDAC_TSETTLE_HIGH			(QSERDES_RX + 0xfc)

#define QSERDES_RX_RX_IDAC_MEASURE_TIME			(QSERDES_RX + 0x100)

#define QSERDES_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1		(QSERDES_RX + 0x110)

#define QSERDES_RX_RX_OFFSET_ADAPTOR_CNTRL2		(QSERDES_RX + 0x114)

#define QSERDES_RX_SIGDET_CNTRL				(QSERDES_RX + 0x11c)

#define QSERDES_RX_SIGDET_DEGLITCH_CNTRL		(QSERDES_RX + 0x124)

#define QSERDES_RX_RX_BAND				(QSERDES_RX + 0x128)

#define QSERDES_RX_RX_MODE_00_LOW			(QSERDES_RX + 0x15c)

#define QSERDES_RX_RX_MODE_00_HIGH			(QSERDES_RX + 0x160)

#define QSERDES_RX_RX_MODE_00_HIGH2			(QSERDES_RX + 0x164)

#define QSERDES_RX_RX_MODE_00_HIGH3			(QSERDES_RX + 0x168)

#define QSERDES_RX_RX_MODE_00_HIGH4			(QSERDES_RX + 0x16c)

#define QSERDES_RX_RX_MODE_01_LOW			(QSERDES_RX + 0x170)

#define QSERDES_RX_RX_MODE_01_HIGH			(QSERDES_RX + 0x174)

#define QSERDES_RX_RX_MODE_01_HIGH2			(QSERDES_RX + 0x178)

#define QSERDES_RX_RX_MODE_01_HIGH3			(QSERDES_RX + 0x17c)

#define QSERDES_RX_RX_MODE_01_HIGH4			(QSERDES_RX + 0x180)

#define QSERDES_RX_RX_MODE_10_LOW			(QSERDES_RX + 0x184)

#define QSERDES_RX_RX_MODE_10_HIGH			(QSERDES_RX + 0x188)

#define QSERDES_RX_RX_MODE_10_HIGH2			(QSERDES_RX + 0x18c)

#define QSERDES_RX_RX_MODE_10_HIGH3			(QSERDES_RX + 0x190)

#define QSERDES_RX_RX_MODE_10_HIGH4			(QSERDES_RX + 0x194)

#define QSERDES_RX_DCC_CTRL1				(QSERDES_RX + 0x1a8)



#define QSERDES_TX					0x400

#define QSERDES_TX_TX_BAND				(QSERDES_TX + 0x24)

#define QSERDES_TX_SLEW_CNTL				(QSERDES_TX + 0x28)

#define QSERDES_TX_RES_CODE_LANE_OFFSET_TX		(QSERDES_TX + 0x3c)

#define QSERDES_TX_RES_CODE_LANE_OFFSET_RX		(QSERDES_TX + 0x40)

#define QSERDES_TX_LANE_MODE_1				(QSERDES_TX + 0x84)

#define QSERDES_TX_LANE_MODE_3				(QSERDES_TX + 0x8c)

#define QSERDES_TX_RCV_DETECT_LVL_2			(QSERDES_TX + 0xa4)

#define QSERDES_TX_TRAN_DRVR_EMP_EN			(QSERDES_TX + 0xc0)



#define QSERDES_PCS					0xC00

#define QSERDES_PCS					0xc00



#define QSERDES_PCS_PHY_START				(QSERDES_PCS + 0x0)

#define QSERDES_PCS_POWER_DOWN_CONTROL			(QSERDES_PCS + 0x4)

#define QSERDES_PCS_SW_RESET				(QSERDES_PCS + 0x8)
@@ -115,77 +46,77 @@ static void qcom_dwmac_sgmii_phy_init_1g(struct regmap *regmap) 
	regmap_write(regmap, QSERDES_PCS_SW_RESET, 0x01);

	regmap_write(regmap, QSERDES_PCS_POWER_DOWN_CONTROL, 0x01);



	regmap_write(regmap, QSERDES_COM_PLL_IVCO, 0x0F);

	regmap_write(regmap, QSERDES_COM_CP_CTRL_MODE0, 0x06);

	regmap_write(regmap, QSERDES_COM_PLL_RCTRL_MODE0, 0x16);

	regmap_write(regmap, QSERDES_COM_PLL_CCTRL_MODE0, 0x36);

	regmap_write(regmap, QSERDES_COM_SYSCLK_EN_SEL, 0x1A);

	regmap_write(regmap, QSERDES_COM_LOCK_CMP1_MODE0, 0x0A);

	regmap_write(regmap, QSERDES_COM_LOCK_CMP2_MODE0, 0x1A);

	regmap_write(regmap, QSERDES_COM_DEC_START_MODE0, 0x82);

	regmap_write(regmap, QSERDES_COM_DIV_FRAC_START1_MODE0, 0x55);

	regmap_write(regmap, QSERDES_COM_DIV_FRAC_START2_MODE0, 0x55);

	regmap_write(regmap, QSERDES_COM_DIV_FRAC_START3_MODE0, 0x03);

	regmap_write(regmap, QSERDES_COM_VCO_TUNE1_MODE0, 0x24);



	regmap_write(regmap, QSERDES_COM_VCO_TUNE2_MODE0, 0x02);

	regmap_write(regmap, QSERDES_COM_VCO_TUNE_INITVAL2, 0x00);

	regmap_write(regmap, QSERDES_COM_HSCLK_SEL, 0x04);

	regmap_write(regmap, QSERDES_COM_HSCLK_HS_SWITCH_SEL, 0x00);

	regmap_write(regmap, QSERDES_COM_CORECLK_DIV_MODE0, 0x0A);

	regmap_write(regmap, QSERDES_COM_CORE_CLK_EN, 0x00);

	regmap_write(regmap, QSERDES_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0xB9);

	regmap_write(regmap, QSERDES_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1E);

	regmap_write(regmap, QSERDES_COM_BIN_VCOCAL_HSCLK_SEL, 0x11);



	regmap_write(regmap, QSERDES_TX_TX_BAND, 0x05);

	regmap_write(regmap, QSERDES_TX_SLEW_CNTL, 0x0A);

	regmap_write(regmap, QSERDES_TX_RES_CODE_LANE_OFFSET_TX, 0x09);

	regmap_write(regmap, QSERDES_TX_RES_CODE_LANE_OFFSET_RX, 0x09);

	regmap_write(regmap, QSERDES_TX_LANE_MODE_1, 0x05);

	regmap_write(regmap, QSERDES_TX_LANE_MODE_3, 0x00);

	regmap_write(regmap, QSERDES_TX_RCV_DETECT_LVL_2, 0x12);

	regmap_write(regmap, QSERDES_TX_TRAN_DRVR_EMP_EN, 0x0C);



	regmap_write(regmap, QSERDES_RX_UCDR_FO_GAIN, 0x0A);

	regmap_write(regmap, QSERDES_RX_UCDR_SO_GAIN, 0x06);

	regmap_write(regmap, QSERDES_RX_UCDR_FASTLOCK_FO_GAIN, 0x0A);

	regmap_write(regmap, QSERDES_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7F);

	regmap_write(regmap, QSERDES_RX_UCDR_FASTLOCK_COUNT_LOW, 0x00);

	regmap_write(regmap, QSERDES_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x01);

	regmap_write(regmap, QSERDES_RX_UCDR_PI_CONTROLS, 0x81);

	regmap_write(regmap, QSERDES_RX_UCDR_PI_CTRL2, 0x80);

	regmap_write(regmap, QSERDES_RX_RX_TERM_BW, 0x04);

	regmap_write(regmap, QSERDES_RX_VGA_CAL_CNTRL2, 0x08);

	regmap_write(regmap, QSERDES_RX_GM_CAL, 0x0F);

	regmap_write(regmap, QSERDES_RX_RX_EQU_ADAPTOR_CNTRL1, 0x04);

	regmap_write(regmap, QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2, 0x00);

	regmap_write(regmap, QSERDES_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4A);

	regmap_write(regmap, QSERDES_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0A);

	regmap_write(regmap, QSERDES_RX_RX_IDAC_TSETTLE_LOW, 0x80);

	regmap_write(regmap, QSERDES_RX_RX_IDAC_TSETTLE_HIGH, 0x01);

	regmap_write(regmap, QSERDES_RX_RX_IDAC_MEASURE_TIME, 0x20);

	regmap_write(regmap, QSERDES_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x17);

	regmap_write(regmap, QSERDES_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x00);

	regmap_write(regmap, QSERDES_RX_SIGDET_CNTRL, 0x0F);

	regmap_write(regmap, QSERDES_RX_SIGDET_DEGLITCH_CNTRL, 0x1E);

	regmap_write(regmap, QSERDES_RX_RX_BAND, 0x05);

	regmap_write(regmap, QSERDES_RX_RX_MODE_00_LOW, 0xE0);

	regmap_write(regmap, QSERDES_RX_RX_MODE_00_HIGH, 0xC8);

	regmap_write(regmap, QSERDES_RX_RX_MODE_00_HIGH2, 0xC8);

	regmap_write(regmap, QSERDES_RX_RX_MODE_00_HIGH3, 0x09);

	regmap_write(regmap, QSERDES_RX_RX_MODE_00_HIGH4, 0xB1);

	regmap_write(regmap, QSERDES_RX_RX_MODE_01_LOW, 0xE0);

	regmap_write(regmap, QSERDES_RX_RX_MODE_01_HIGH, 0xC8);

	regmap_write(regmap, QSERDES_RX_RX_MODE_01_HIGH2, 0xC8);

	regmap_write(regmap, QSERDES_RX_RX_MODE_01_HIGH3, 0x09);

	regmap_write(regmap, QSERDES_RX_RX_MODE_01_HIGH4, 0xB1);

	regmap_write(regmap, QSERDES_RX_RX_MODE_10_LOW, 0xE0);

	regmap_write(regmap, QSERDES_RX_RX_MODE_10_HIGH, 0xC8);

	regmap_write(regmap, QSERDES_RX_RX_MODE_10_HIGH2, 0xC8);

	regmap_write(regmap, QSERDES_RX_RX_MODE_10_HIGH3, 0x3B);

	regmap_write(regmap, QSERDES_RX_RX_MODE_10_HIGH4, 0xB7);

	regmap_write(regmap, QSERDES_RX_DCC_CTRL1, 0x0C);

	regmap_write(regmap, QSERDES_QMP_PLL + QSERDES_V5_COM_PLL_IVCO, 0x0F);

	regmap_write(regmap, QSERDES_QMP_PLL + QSERDES_V5_COM_CP_CTRL_MODE0, 0x06);

	regmap_write(regmap, QSERDES_QMP_PLL + QSERDES_V5_COM_PLL_RCTRL_MODE0, 0x16);

	regmap_write(regmap, QSERDES_QMP_PLL + QSERDES_V5_COM_PLL_CCTRL_MODE0, 0x36);

	regmap_write(regmap, QSERDES_QMP_PLL + QSERDES_V5_COM_SYSCLK_EN_SEL, 0x1A);

	regmap_write(regmap, QSERDES_QMP_PLL + QSERDES_V5_COM_LOCK_CMP1_MODE0, 0x0A);

	regmap_write(regmap, QSERDES_QMP_PLL + QSERDES_V5_COM_LOCK_CMP2_MODE0, 0x1A);

	regmap_write(regmap, QSERDES_QMP_PLL + QSERDES_V5_COM_DEC_START_MODE0, 0x82);

	regmap_write(regmap, QSERDES_QMP_PLL + QSERDES_V5_COM_DIV_FRAC_START1_MODE0, 0x55);

	regmap_write(regmap, QSERDES_QMP_PLL + QSERDES_V5_COM_DIV_FRAC_START2_MODE0, 0x55);

	regmap_write(regmap, QSERDES_QMP_PLL + QSERDES_V5_COM_DIV_FRAC_START3_MODE0, 0x03);

	regmap_write(regmap, QSERDES_QMP_PLL + QSERDES_V5_COM_VCO_TUNE1_MODE0, 0x24);



	regmap_write(regmap, QSERDES_QMP_PLL + QSERDES_V5_COM_VCO_TUNE2_MODE0, 0x02);

	regmap_write(regmap, QSERDES_QMP_PLL + QSERDES_V5_COM_VCO_TUNE_INITVAL2, 0x00);

	regmap_write(regmap, QSERDES_QMP_PLL + QSERDES_V5_COM_HSCLK_SEL, 0x04);

	regmap_write(regmap, QSERDES_QMP_PLL + QSERDES_V5_COM_HSCLK_HS_SWITCH_SEL, 0x00);

	regmap_write(regmap, QSERDES_QMP_PLL + QSERDES_V5_COM_CORECLK_DIV_MODE0, 0x0A);

	regmap_write(regmap, QSERDES_QMP_PLL + QSERDES_V5_COM_CORE_CLK_EN, 0x00);

	regmap_write(regmap, QSERDES_QMP_PLL + QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0xB9);

	regmap_write(regmap, QSERDES_QMP_PLL + QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1E);

	regmap_write(regmap, QSERDES_QMP_PLL + QSERDES_V5_COM_BIN_VCOCAL_HSCLK_SEL, 0x11);



	regmap_write(regmap, QSERDES_TX + QSERDES_V5_TX_TX_BAND, 0x05);

	regmap_write(regmap, QSERDES_TX + QSERDES_V5_TX_SLEW_CNTL, 0x0A);

	regmap_write(regmap, QSERDES_TX + QSERDES_V5_TX_RES_CODE_LANE_OFFSET_TX, 0x09);

	regmap_write(regmap, QSERDES_TX + QSERDES_V5_TX_RES_CODE_LANE_OFFSET_RX, 0x09);

	regmap_write(regmap, QSERDES_TX + QSERDES_V5_TX_LANE_MODE_1, 0x05);

	regmap_write(regmap, QSERDES_TX + QSERDES_V5_TX_LANE_MODE_3, 0x00);

	regmap_write(regmap, QSERDES_TX + QSERDES_V5_TX_RCV_DETECT_LVL_2, 0x12);

	regmap_write(regmap, QSERDES_TX + QSERDES_V5_TX_TRAN_DRVR_EMP_EN, 0x0C);



	regmap_write(regmap, QSERDES_RX + QSERDES_V5_RX_UCDR_FO_GAIN, 0x0A);

	regmap_write(regmap, QSERDES_RX + QSERDES_V5_RX_UCDR_SO_GAIN, 0x06);

	regmap_write(regmap, QSERDES_RX + QSERDES_V5_RX_UCDR_FASTLOCK_FO_GAIN, 0x0A);

	regmap_write(regmap, QSERDES_RX + QSERDES_V5_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7F);

	regmap_write(regmap, QSERDES_RX + QSERDES_V5_RX_UCDR_FASTLOCK_COUNT_LOW, 0x00);

	regmap_write(regmap, QSERDES_RX + QSERDES_V5_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x01);

	regmap_write(regmap, QSERDES_RX + QSERDES_V5_RX_UCDR_PI_CONTROLS, 0x81);

	regmap_write(regmap, QSERDES_RX + QSERDES_V5_RX_UCDR_PI_CTRL2, 0x80);

	regmap_write(regmap, QSERDES_RX + QSERDES_V5_RX_RX_TERM_BW, 0x04);

	regmap_write(regmap, QSERDES_RX + QSERDES_V5_RX_VGA_CAL_CNTRL2, 0x08);

	regmap_write(regmap, QSERDES_RX + QSERDES_V5_RX_GM_CAL, 0x0F);

	regmap_write(regmap, QSERDES_RX + QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL1, 0x04);

	regmap_write(regmap, QSERDES_RX + QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL2, 0x00);

	regmap_write(regmap, QSERDES_RX + QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4A);

	regmap_write(regmap, QSERDES_RX + QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0A);

	regmap_write(regmap, QSERDES_RX + QSERDES_V5_RX_RX_IDAC_TSETTLE_LOW, 0x80);

	regmap_write(regmap, QSERDES_RX + QSERDES_V5_RX_RX_IDAC_TSETTLE_HIGH, 0x01);

	regmap_write(regmap, QSERDES_RX + QSERDES_V5_RX_RX_IDAC_MEASURE_TIME, 0x20);

	regmap_write(regmap, QSERDES_RX + QSERDES_V5_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x17);

	regmap_write(regmap, QSERDES_RX + QSERDES_V5_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x00);

	regmap_write(regmap, QSERDES_RX + QSERDES_V5_RX_SIGDET_CNTRL, 0x0F);

	regmap_write(regmap, QSERDES_RX + QSERDES_V5_RX_SIGDET_DEGLITCH_CNTRL, 0x1E);

	regmap_write(regmap, QSERDES_RX + QSERDES_V5_RX_RX_BAND, 0x05);

	regmap_write(regmap, QSERDES_RX + QSERDES_V5_RX_RX_MODE_00_LOW, 0xE0);

	regmap_write(regmap, QSERDES_RX + QSERDES_V5_RX_RX_MODE_00_HIGH, 0xC8);

	regmap_write(regmap, QSERDES_RX + QSERDES_V5_RX_RX_MODE_00_HIGH2, 0xC8);

	regmap_write(regmap, QSERDES_RX + QSERDES_V5_RX_RX_MODE_00_HIGH3, 0x09);

	regmap_write(regmap, QSERDES_RX + QSERDES_V5_RX_RX_MODE_00_HIGH4, 0xB1);

	regmap_write(regmap, QSERDES_RX + QSERDES_V5_RX_RX_MODE_01_LOW, 0xE0);

	regmap_write(regmap, QSERDES_RX + QSERDES_V5_RX_RX_MODE_01_HIGH, 0xC8);

	regmap_write(regmap, QSERDES_RX + QSERDES_V5_RX_RX_MODE_01_HIGH2, 0xC8);

	regmap_write(regmap, QSERDES_RX + QSERDES_V5_RX_RX_MODE_01_HIGH3, 0x09);

	regmap_write(regmap, QSERDES_RX + QSERDES_V5_RX_RX_MODE_01_HIGH4, 0xB1);

	regmap_write(regmap, QSERDES_RX + QSERDES_V5_RX_RX_MODE_10_LOW, 0xE0);

	regmap_write(regmap, QSERDES_RX + QSERDES_V5_RX_RX_MODE_10_HIGH, 0xC8);

	regmap_write(regmap, QSERDES_RX + QSERDES_V5_RX_RX_MODE_10_HIGH2, 0xC8);

	regmap_write(regmap, QSERDES_RX + QSERDES_V5_RX_RX_MODE_10_HIGH3, 0x3B);

	regmap_write(regmap, QSERDES_RX + QSERDES_V5_RX_RX_MODE_10_HIGH4, 0xB7);

	regmap_write(regmap, QSERDES_RX + QSERDES_V5_RX_DCC_CTRL1, 0x0C);



	regmap_write(regmap, QSERDES_PCS_LINE_RESET_TIME, 0x0C);

	regmap_write(regmap, QSERDES_PCS_TX_LARGE_AMP_DRV_LVL, 0x1F);
@@ -203,77 +134,77 @@ static void qcom_dwmac_sgmii_phy_init_2p5g(struct regmap *regmap) 
	regmap_write(regmap, QSERDES_PCS_SW_RESET, 0x01);

	regmap_write(regmap, QSERDES_PCS_POWER_DOWN_CONTROL, 0x01);



	regmap_write(regmap, QSERDES_COM_PLL_IVCO, 0x0F);

	regmap_write(regmap, QSERDES_COM_CP_CTRL_MODE0, 0x06);

	regmap_write(regmap, QSERDES_COM_PLL_RCTRL_MODE0, 0x16);

	regmap_write(regmap, QSERDES_COM_PLL_CCTRL_MODE0, 0x36);

	regmap_write(regmap, QSERDES_COM_SYSCLK_EN_SEL, 0x1A);

	regmap_write(regmap, QSERDES_COM_LOCK_CMP1_MODE0, 0x1A);

	regmap_write(regmap, QSERDES_COM_LOCK_CMP2_MODE0, 0x41);

	regmap_write(regmap, QSERDES_COM_DEC_START_MODE0, 0x7A);

	regmap_write(regmap, QSERDES_COM_DIV_FRAC_START1_MODE0, 0x00);

	regmap_write(regmap, QSERDES_COM_DIV_FRAC_START2_MODE0, 0x20);

	regmap_write(regmap, QSERDES_COM_DIV_FRAC_START3_MODE0, 0x01);

	regmap_write(regmap, QSERDES_COM_VCO_TUNE1_MODE0, 0xA1);



	regmap_write(regmap, QSERDES_COM_VCO_TUNE2_MODE0, 0x02);

	regmap_write(regmap, QSERDES_COM_VCO_TUNE_INITVAL2, 0x00);

	regmap_write(regmap, QSERDES_COM_HSCLK_SEL, 0x03);

	regmap_write(regmap, QSERDES_COM_HSCLK_HS_SWITCH_SEL, 0x00);

	regmap_write(regmap, QSERDES_COM_CORECLK_DIV_MODE0, 0x05);

	regmap_write(regmap, QSERDES_COM_CORE_CLK_EN, 0x00);

	regmap_write(regmap, QSERDES_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0xCD);

	regmap_write(regmap, QSERDES_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1C);

	regmap_write(regmap, QSERDES_COM_BIN_VCOCAL_HSCLK_SEL, 0x11);



	regmap_write(regmap, QSERDES_TX_TX_BAND, 0x04);

	regmap_write(regmap, QSERDES_TX_SLEW_CNTL, 0x0A);

	regmap_write(regmap, QSERDES_TX_RES_CODE_LANE_OFFSET_TX, 0x09);

	regmap_write(regmap, QSERDES_TX_RES_CODE_LANE_OFFSET_RX, 0x02);

	regmap_write(regmap, QSERDES_TX_LANE_MODE_1, 0x05);

	regmap_write(regmap, QSERDES_TX_LANE_MODE_3, 0x00);

	regmap_write(regmap, QSERDES_TX_RCV_DETECT_LVL_2, 0x12);

	regmap_write(regmap, QSERDES_TX_TRAN_DRVR_EMP_EN, 0x0C);



	regmap_write(regmap, QSERDES_RX_UCDR_FO_GAIN, 0x0A);

	regmap_write(regmap, QSERDES_RX_UCDR_SO_GAIN, 0x06);

	regmap_write(regmap, QSERDES_RX_UCDR_FASTLOCK_FO_GAIN, 0x0A);

	regmap_write(regmap, QSERDES_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7F);

	regmap_write(regmap, QSERDES_RX_UCDR_FASTLOCK_COUNT_LOW, 0x00);

	regmap_write(regmap, QSERDES_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x01);

	regmap_write(regmap, QSERDES_RX_UCDR_PI_CONTROLS, 0x81);

	regmap_write(regmap, QSERDES_RX_UCDR_PI_CTRL2, 0x80);

	regmap_write(regmap, QSERDES_RX_RX_TERM_BW, 0x00);

	regmap_write(regmap, QSERDES_RX_VGA_CAL_CNTRL2, 0x08);

	regmap_write(regmap, QSERDES_RX_GM_CAL, 0x0F);

	regmap_write(regmap, QSERDES_RX_RX_EQU_ADAPTOR_CNTRL1, 0x04);

	regmap_write(regmap, QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2, 0x00);

	regmap_write(regmap, QSERDES_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4A);

	regmap_write(regmap, QSERDES_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0A);

	regmap_write(regmap, QSERDES_RX_RX_IDAC_TSETTLE_LOW, 0x80);

	regmap_write(regmap, QSERDES_RX_RX_IDAC_TSETTLE_HIGH, 0x01);

	regmap_write(regmap, QSERDES_RX_RX_IDAC_MEASURE_TIME, 0x20);

	regmap_write(regmap, QSERDES_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x17);

	regmap_write(regmap, QSERDES_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x00);

	regmap_write(regmap, QSERDES_RX_SIGDET_CNTRL, 0x0F);

	regmap_write(regmap, QSERDES_RX_SIGDET_DEGLITCH_CNTRL, 0x1E);

	regmap_write(regmap, QSERDES_RX_RX_BAND, 0x18);

	regmap_write(regmap, QSERDES_RX_RX_MODE_00_LOW, 0x18);

	regmap_write(regmap, QSERDES_RX_RX_MODE_00_HIGH, 0xC8);

	regmap_write(regmap, QSERDES_RX_RX_MODE_00_HIGH2, 0xC8);

	regmap_write(regmap, QSERDES_RX_RX_MODE_00_HIGH3, 0x0C);

	regmap_write(regmap, QSERDES_RX_RX_MODE_00_HIGH4, 0xB8);

	regmap_write(regmap, QSERDES_RX_RX_MODE_01_LOW, 0xE0);

	regmap_write(regmap, QSERDES_RX_RX_MODE_01_HIGH, 0xC8);

	regmap_write(regmap, QSERDES_RX_RX_MODE_01_HIGH2, 0xC8);

	regmap_write(regmap, QSERDES_RX_RX_MODE_01_HIGH3, 0x09);

	regmap_write(regmap, QSERDES_RX_RX_MODE_01_HIGH4, 0xB1);

	regmap_write(regmap, QSERDES_RX_RX_MODE_10_LOW, 0xE0);

	regmap_write(regmap, QSERDES_RX_RX_MODE_10_HIGH, 0xC8);

	regmap_write(regmap, QSERDES_RX_RX_MODE_10_HIGH2, 0xC8);

	regmap_write(regmap, QSERDES_RX_RX_MODE_10_HIGH3, 0x3B);

	regmap_write(regmap, QSERDES_RX_RX_MODE_10_HIGH4, 0xB7);

	regmap_write(regmap, QSERDES_RX_DCC_CTRL1, 0x0C);

	regmap_write(regmap, QSERDES_QMP_PLL + QSERDES_V5_COM_PLL_IVCO, 0x0F);

	regmap_write(regmap, QSERDES_QMP_PLL + QSERDES_V5_COM_CP_CTRL_MODE0, 0x06);

	regmap_write(regmap, QSERDES_QMP_PLL + QSERDES_V5_COM_PLL_RCTRL_MODE0, 0x16);

	regmap_write(regmap, QSERDES_QMP_PLL + QSERDES_V5_COM_PLL_CCTRL_MODE0, 0x36);

	regmap_write(regmap, QSERDES_QMP_PLL + QSERDES_V5_COM_SYSCLK_EN_SEL, 0x1A);

	regmap_write(regmap, QSERDES_QMP_PLL + QSERDES_V5_COM_LOCK_CMP1_MODE0, 0x1A);

	regmap_write(regmap, QSERDES_QMP_PLL + QSERDES_V5_COM_LOCK_CMP2_MODE0, 0x41);

	regmap_write(regmap, QSERDES_QMP_PLL + QSERDES_V5_COM_DEC_START_MODE0, 0x7A);

	regmap_write(regmap, QSERDES_QMP_PLL + QSERDES_V5_COM_DIV_FRAC_START1_MODE0, 0x00);

	regmap_write(regmap, QSERDES_QMP_PLL + QSERDES_V5_COM_DIV_FRAC_START2_MODE0, 0x20);

	regmap_write(regmap, QSERDES_QMP_PLL + QSERDES_V5_COM_DIV_FRAC_START3_MODE0, 0x01);

	regmap_write(regmap, QSERDES_QMP_PLL + QSERDES_V5_COM_VCO_TUNE1_MODE0, 0xA1);



	regmap_write(regmap, QSERDES_QMP_PLL + QSERDES_V5_COM_VCO_TUNE2_MODE0, 0x02);

	regmap_write(regmap, QSERDES_QMP_PLL + QSERDES_V5_COM_VCO_TUNE_INITVAL2, 0x00);

	regmap_write(regmap, QSERDES_QMP_PLL + QSERDES_V5_COM_HSCLK_SEL, 0x03);

	regmap_write(regmap, QSERDES_QMP_PLL + QSERDES_V5_COM_HSCLK_HS_SWITCH_SEL, 0x00);

	regmap_write(regmap, QSERDES_QMP_PLL + QSERDES_V5_COM_CORECLK_DIV_MODE0, 0x05);

	regmap_write(regmap, QSERDES_QMP_PLL + QSERDES_V5_COM_CORE_CLK_EN, 0x00);

	regmap_write(regmap, QSERDES_QMP_PLL + QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0xCD);

	regmap_write(regmap, QSERDES_QMP_PLL + QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1C);

	regmap_write(regmap, QSERDES_QMP_PLL + QSERDES_V5_COM_BIN_VCOCAL_HSCLK_SEL, 0x11);



	regmap_write(regmap, QSERDES_TX + QSERDES_V5_TX_TX_BAND, 0x04);

	regmap_write(regmap, QSERDES_TX + QSERDES_V5_TX_SLEW_CNTL, 0x0A);

	regmap_write(regmap, QSERDES_TX + QSERDES_V5_TX_RES_CODE_LANE_OFFSET_TX, 0x09);

	regmap_write(regmap, QSERDES_TX + QSERDES_V5_TX_RES_CODE_LANE_OFFSET_RX, 0x02);

	regmap_write(regmap, QSERDES_TX + QSERDES_V5_TX_LANE_MODE_1, 0x05);

	regmap_write(regmap, QSERDES_TX + QSERDES_V5_TX_LANE_MODE_3, 0x00);

	regmap_write(regmap, QSERDES_TX + QSERDES_V5_TX_RCV_DETECT_LVL_2, 0x12);

	regmap_write(regmap, QSERDES_TX + QSERDES_V5_TX_TRAN_DRVR_EMP_EN, 0x0C);



	regmap_write(regmap, QSERDES_RX + QSERDES_V5_RX_UCDR_FO_GAIN, 0x0A);

	regmap_write(regmap, QSERDES_RX + QSERDES_V5_RX_UCDR_SO_GAIN, 0x06);

	regmap_write(regmap, QSERDES_RX + QSERDES_V5_RX_UCDR_FASTLOCK_FO_GAIN, 0x0A);

	regmap_write(regmap, QSERDES_RX + QSERDES_V5_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7F);

	regmap_write(regmap, QSERDES_RX + QSERDES_V5_RX_UCDR_FASTLOCK_COUNT_LOW, 0x00);

	regmap_write(regmap, QSERDES_RX + QSERDES_V5_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x01);

	regmap_write(regmap, QSERDES_RX + QSERDES_V5_RX_UCDR_PI_CONTROLS, 0x81);

	regmap_write(regmap, QSERDES_RX + QSERDES_V5_RX_UCDR_PI_CTRL2, 0x80);

	regmap_write(regmap, QSERDES_RX + QSERDES_V5_RX_RX_TERM_BW, 0x00);

	regmap_write(regmap, QSERDES_RX + QSERDES_V5_RX_VGA_CAL_CNTRL2, 0x08);

	regmap_write(regmap, QSERDES_RX + QSERDES_V5_RX_GM_CAL, 0x0F);

	regmap_write(regmap, QSERDES_RX + QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL1, 0x04);

	regmap_write(regmap, QSERDES_RX + QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL2, 0x00);

	regmap_write(regmap, QSERDES_RX + QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4A);

	regmap_write(regmap, QSERDES_RX + QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0A);

	regmap_write(regmap, QSERDES_RX + QSERDES_V5_RX_RX_IDAC_TSETTLE_LOW, 0x80);

	regmap_write(regmap, QSERDES_RX + QSERDES_V5_RX_RX_IDAC_TSETTLE_HIGH, 0x01);

	regmap_write(regmap, QSERDES_RX + QSERDES_V5_RX_RX_IDAC_MEASURE_TIME, 0x20);

	regmap_write(regmap, QSERDES_RX + QSERDES_V5_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x17);

	regmap_write(regmap, QSERDES_RX + QSERDES_V5_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x00);

	regmap_write(regmap, QSERDES_RX + QSERDES_V5_RX_SIGDET_CNTRL, 0x0F);

	regmap_write(regmap, QSERDES_RX + QSERDES_V5_RX_SIGDET_DEGLITCH_CNTRL, 0x1E);

	regmap_write(regmap, QSERDES_RX + QSERDES_V5_RX_RX_BAND, 0x18);

	regmap_write(regmap, QSERDES_RX + QSERDES_V5_RX_RX_MODE_00_LOW, 0x18);

	regmap_write(regmap, QSERDES_RX + QSERDES_V5_RX_RX_MODE_00_HIGH, 0xC8);

	regmap_write(regmap, QSERDES_RX + QSERDES_V5_RX_RX_MODE_00_HIGH2, 0xC8);

	regmap_write(regmap, QSERDES_RX + QSERDES_V5_RX_RX_MODE_00_HIGH3, 0x0C);

	regmap_write(regmap, QSERDES_RX + QSERDES_V5_RX_RX_MODE_00_HIGH4, 0xB8);

	regmap_write(regmap, QSERDES_RX + QSERDES_V5_RX_RX_MODE_01_LOW, 0xE0);

	regmap_write(regmap, QSERDES_RX + QSERDES_V5_RX_RX_MODE_01_HIGH, 0xC8);

	regmap_write(regmap, QSERDES_RX + QSERDES_V5_RX_RX_MODE_01_HIGH2, 0xC8);

	regmap_write(regmap, QSERDES_RX + QSERDES_V5_RX_RX_MODE_01_HIGH3, 0x09);

	regmap_write(regmap, QSERDES_RX + QSERDES_V5_RX_RX_MODE_01_HIGH4, 0xB1);

	regmap_write(regmap, QSERDES_RX + QSERDES_V5_RX_RX_MODE_10_LOW, 0xE0);

	regmap_write(regmap, QSERDES_RX + QSERDES_V5_RX_RX_MODE_10_HIGH, 0xC8);

	regmap_write(regmap, QSERDES_RX + QSERDES_V5_RX_RX_MODE_10_HIGH2, 0xC8);

	regmap_write(regmap, QSERDES_RX + QSERDES_V5_RX_RX_MODE_10_HIGH3, 0x3B);

	regmap_write(regmap, QSERDES_RX + QSERDES_V5_RX_RX_MODE_10_HIGH4, 0xB7);

	regmap_write(regmap, QSERDES_RX + QSERDES_V5_RX_DCC_CTRL1, 0x0C);



	regmap_write(regmap, QSERDES_PCS_LINE_RESET_TIME, 0x0C);

	regmap_write(regmap, QSERDES_PCS_TX_LARGE_AMP_DRV_LVL, 0x1F);
@@ -313,7 +244,7 @@ static int qcom_dwmac_sgmii_phy_calibrate(struct phy *phy) 
	}



	if (qcom_dwmac_sgmii_phy_poll_status(data->regmap,

					     QSERDES_COM_C_READY_STATUS,

					     QSERDES_QMP_PLL + QSERDES_V5_COM_C_READY_STATUS,

					     QSERDES_COM_C_READY)) {

		dev_err(dev, "QSERDES_COM_C_READY_STATUS timed-out");

		return -ETIMEDOUT;
@@ -334,7 +265,7 @@ static int qcom_dwmac_sgmii_phy_calibrate(struct phy *phy) 
	}



	if (qcom_dwmac_sgmii_phy_poll_status(data->regmap,

					     QSERDES_COM_CMN_STATUS,

					     QSERDES_QMP_PLL + QSERDES_V5_COM_CMN_STATUS,

					     QSERDES_COM_C_PLL_LOCKED)) {

		dev_err(dev, "PLL Lock Status timed-out");

		return -ETIMEDOUT;