Commit df947ad4 authored by Stephen Boyd's avatar Stephen Boyd
Browse files

Merge tag 'v6.12-rockchip-clk1' of... 

Merge tag 'v6.12-rockchip-clk1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into clk-rockchip

Pull Rockchip clk driver updates from Heiko Stübner:

 - Get rid of CLK_NR_CLKS defines in Rockchip DT binding headers
 - New clock controller driver for the rk3576
 - Some fixes for rk3228 and rk3588

* tag 'v6.12-rockchip-clk1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip:
  clk: rockchip: fix error for unknown clocks
  clk: rockchip: rk3588: drop unused code
  clk: rockchip: Add clock controller for the RK3576
  clk: rockchip: Add new pll type pll_rk3588_ddr
  dt-bindings: clock, reset: Add support for rk3576
  dt-bindings: clock: rockchip,rk3588-cru: drop unneeded assigned-clocks
  clk: rockchip: rk3588: Fix 32k clock name for pmu_24m_32k_100m_src_p
  dt-bindings: clock: rockchip: remove CLK_NR_CLKS and CLKPMU_NR_CLKS
  clk: rockchip: rk3399: Drop CLK_NR_CLKS CLKPMU_NR_CLKS usage
  clk: rockchip: rk3368: Drop CLK_NR_CLKS usage
  clk: rockchip: rk3328: Drop CLK_NR_CLKS usage
  clk: rockchip: rk3308: Drop CLK_NR_CLKS usage
  clk: rockchip: rk3288: Drop CLK_NR_CLKS usage
  clk: rockchip: rk3228: Drop CLK_NR_CLKS usage
  clk: rockchip: rk3036: Drop CLK_NR_CLKS usage
  clk: rockchip: px30: Drop CLK_NR_CLKS CLKPMU_NR_CLKS usage
  clk: rockchip: Set parent rate for DCLK_VOP clock on RK3228
parents 8400291e 12fd64ba

Documentation/devicetree/bindings/clock/rockchip,rk3576-cru.yaml

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# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause

%YAML 1.2

---

$id: http://devicetree.org/schemas/clock/rockchip,rk3576-cru.yaml#

$schema: http://devicetree.org/meta-schemas/core.yaml#



title: Rockchip rk3576 Family Clock and Reset Control Module



maintainers:

  - Elaine Zhang <zhangqing@rock-chips.com>

  - Heiko Stuebner <heiko@sntech.de>

  - Detlev Casanova <detlev.casanova@collabora.com>



description:

  The RK3576 clock controller generates the clock and also implements a reset

  controller for SoC peripherals. For example it provides SCLK_UART2 and

  PCLK_UART2, as well as SRST_P_UART2 and SRST_S_UART2 for the second UART

  module.



properties:

  compatible:

    const: rockchip,rk3576-cru



  reg:

    maxItems: 1



  "#clock-cells":

    const: 1



  "#reset-cells":

    const: 1



  clocks:

    maxItems: 2



  clock-names:

    items:

      - const: xin24m

      - const: xin32k



required:

  - compatible

  - reg

  - "#clock-cells"

  - "#reset-cells"



additionalProperties: false



examples:

  - |

    clock-controller@27200000 {

      compatible = "rockchip,rk3576-cru";

      reg = <0xfd7c0000 0x5c000>;

      #clock-cells = <1>;

      #reset-cells = <1>;

    };

Documentation/devicetree/bindings/clock/rockchip,rk3588-cru.yaml

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@@ -42,10 +42,6 @@ properties: 
      - const: xin24m

      - const: xin32k



  assigned-clocks: true



  assigned-clock-rates: true



  rockchip,grf:

    $ref: /schemas/types.yaml#/definitions/phandle

    description: >

drivers/clk/rockchip/Kconfig

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@@ -100,6 +100,13 @@ config CLK_RK3568 
	help

	  Build the driver for RK3568 Clock Driver.



config CLK_RK3576

	bool "Rockchip RK3576 clock controller support"

	depends on ARM64 || COMPILE_TEST

	default y

	help

	  Build the driver for RK3576 Clock Driver.



config CLK_RK3588

	bool "Rockchip RK3588 clock controller support"

	depends on ARM64 || COMPILE_TEST

drivers/clk/rockchip/Makefile

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@@ -28,4 +28,5 @@ obj-$(CONFIG_CLK_RK3328) += clk-rk3328.o 
obj-$(CONFIG_CLK_RK3368)        += clk-rk3368.o

obj-$(CONFIG_CLK_RK3399)        += clk-rk3399.o

obj-$(CONFIG_CLK_RK3568)	+= clk-rk3568.o

obj-$(CONFIG_CLK_RK3576)	+= clk-rk3576.o rst-rk3576.o

obj-$(CONFIG_CLK_RK3588)	+= clk-rk3588.o rst-rk3588.o

drivers/clk/rockchip/clk-pll.c

+5 −1
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@@ -914,6 +914,9 @@ static unsigned long rockchip_rk3588_pll_recalc_rate(struct clk_hw *hw, unsigned 
	}

	rate64 = rate64 >> cur.s;



	if (pll->type == pll_rk3588_ddr)

		return (unsigned long)rate64 * 2;

	else

		return (unsigned long)rate64;

}
@@ -1167,6 +1170,7 @@ struct clk *rockchip_clk_register_pll(struct rockchip_clk_provider *ctx, 
		break;

	case pll_rk3588:

	case pll_rk3588_core:

	case pll_rk3588_ddr:

		if (!pll->rate_table)

			init.ops = &rockchip_rk3588_pll_clk_norate_ops;

		else