Commit df967019 authored by Gustavo Sousa's avatar Gustavo Sousa Committed by Matt Roper
Browse files

drm/i915/xe3p_lpd: Handle underrun debug bits 

Xe3p_LPD added several bits containing information that can be relevant
to debugging FIFO underruns.  Add the logic necessary to handle them
when reporting underruns.

This was adapted from the initial patch[1] from Sai Teja Pottumuttu.

[1] https://lore.kernel.org/all/20251015-xe3p_lpd-basic-enabling-v1-12-d2d1e26520aa@intel.com/



v2:
  - Handle FBC-related bits in intel_fbc.c. (Ville)
  - Do not use intel_fbc_id_for_pipe (promoted from
    skl_fbc_id_for_pipe), but use pipe's primary plane to get the FBC
    instance. (Ville, Matt)
  - Improve code readability by moving logic specific to logging fields
    of UNDERRUN_DBG1 to a separate function. (Jani)

v3:
  - Use crtc->base.primary instead of cycling through all crtcs

Bspec: 69111, 69561, 74411, 74412
Cc: Jani Nikula <jani.nikula@intel.com>
Cc: Matt Roper <matthew.d.roper@intel.com>
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: default avatarGustavo Sousa <gustavo.sousa@intel.com>
Signed-off-by: default avatarMatt Atwood <matthew.s.atwood@intel.com>
Link: https://patch.msgid.link/20251202012306.9315-5-matthew.s.atwood@intel.com


Signed-off-by: default avatarMatt Roper <matthew.d.roper@intel.com>
parent df5dd52a

drivers/gpu/drm/i915/display/intel_display_device.h

+1 −0
Original line number Diff line number Diff line
@@ -197,6 +197,7 @@ struct intel_display_platforms { 
#define HAS_TRANSCODER(__display, trans)	((DISPLAY_RUNTIME_INFO(__display)->cpu_transcoder_mask & \

						  BIT(trans)) != 0)

#define HAS_UNCOMPRESSED_JOINER(__display)	(DISPLAY_VER(__display) >= 13)

#define HAS_UNDERRUN_DBG_INFO(__display)	(DISPLAY_VER(__display) >= 35)

#define HAS_ULTRAJOINER(__display)	(((__display)->platform.dgfx && \

					  DISPLAY_VER(__display) == 14) && HAS_DSC(__display))

#define HAS_VRR(__display)		(DISPLAY_VER(__display) >= 11)

drivers/gpu/drm/i915/display/intel_display_regs.h

+16 −0
Original line number Diff line number Diff line
@@ -882,6 +882,21 @@ 
#define   PIPE_MISC2_FLIP_INFO_PLANE_SEL_MASK		REG_GENMASK(2, 0) /* tgl+ */

#define   PIPE_MISC2_FLIP_INFO_PLANE_SEL(plane_id)	REG_FIELD_PREP(PIPE_MISC2_FLIP_INFO_PLANE_SEL_MASK, (plane_id))



#define _UNDERRUN_DBG1_A			0x70064

#define _UNDERRUN_DBG1_B			0x71064

#define UNDERRUN_DBG1(pipe)			_MMIO_PIPE(pipe, _UNDERRUN_DBG1_A, _UNDERRUN_DBG1_B)

#define   UNDERRUN_DBUF_BLOCK_NOT_VALID_MASK	REG_GENMASK(29, 24)

#define   UNDERRUN_DDB_EMPTY_MASK		REG_GENMASK(21, 16)

#define   UNDERRUN_DBUF_NOT_FILLED_MASK		REG_GENMASK(13, 8)

#define   UNDERRUN_BELOW_WM0_MASK		REG_GENMASK(5, 0)



#define _UNDERRUN_DBG2_A			0x70068

#define _UNDERRUN_DBG2_B			0x71068

#define UNDERRUN_DBG2(pipe)			_MMIO_PIPE(pipe, _UNDERRUN_DBG2_A, _UNDERRUN_DBG2_B)

#define   UNDERRUN_FRAME_LINE_COUNTERS_FROZEN	REG_BIT(31)

#define   UNDERRUN_PIPE_FRAME_COUNT_MASK	REG_GENMASK(30, 20)

#define   UNDERRUN_LINE_COUNT_MASK		REG_GENMASK(19, 0)



#define DPINVGTT				_MMIO(VLV_DISPLAY_BASE + 0x7002c) /* VLV/CHV only */

#define   DPINVGTT_EN_MASK_CHV				REG_GENMASK(27, 16)

#define   DPINVGTT_EN_MASK_VLV				REG_GENMASK(23, 16)
@@ -1416,6 +1431,7 @@ 


#define GEN12_DCPR_STATUS_1				_MMIO(0x46440)

#define  XELPDP_PMDEMAND_INFLIGHT_STATUS		REG_BIT(26)

#define  XE3P_UNDERRUN_PKGC				REG_BIT(21)



#define FUSE_STRAP		_MMIO(0x42014)

#define   ILK_INTERNAL_GRAPHICS_DISABLE	REG_BIT(31)

drivers/gpu/drm/i915/display/intel_fbc.c

+44 −0
Original line number Diff line number Diff line
@@ -127,6 +127,19 @@ struct intel_fbc { 
	const char *no_fbc_reason;

};



static struct intel_fbc *intel_fbc_for_pipe(struct intel_display *display, enum pipe pipe)

{

	struct intel_crtc *crtc = intel_crtc_for_pipe(display, pipe);

	struct intel_plane *primary = NULL;



	primary = to_intel_plane(crtc->base.primary);



	if (drm_WARN_ON(display->drm, !primary))

		return NULL;



	return primary->fbc;

}



/* plane stride in pixels */

static unsigned int intel_fbc_plane_stride(const struct intel_plane_state *plane_state)

{
@@ -2124,6 +2137,37 @@ void intel_fbc_handle_fifo_underrun_irq(struct intel_display *display) 
		__intel_fbc_handle_fifo_underrun_irq(fbc);

}



/**

 * intel_fbc_read_underrun_dbg_info - Read and log FBC-related FIFO underrun debug info

 * @display: display device instance

 * @pipe: the pipe possibly containing the FBC

 * @log: log the info?

 *

 * If @pipe does not contain an FBC instance, this function bails early.

 * Otherwise, FBC-related FIFO underrun is read and cleared, and then, if @log

 * is true, printed with error level.

 */

void intel_fbc_read_underrun_dbg_info(struct intel_display *display,

				      enum pipe pipe, bool log)

{

	struct intel_fbc *fbc = intel_fbc_for_pipe(display, pipe);

	u32 val;



	if (!fbc)

		return;



	val = intel_de_read(display, FBC_DEBUG_STATUS(fbc->id));

	if (!(val & FBC_UNDERRUN_DECMPR))

		return;



	intel_de_write(display, FBC_DEBUG_STATUS(fbc->id), FBC_UNDERRUN_DECMPR);



	if (log)

		drm_err(display->drm,

			"Pipe %c FIFO underrun info: FBC decompressing\n",

			pipe_name(pipe));

}



/*

 * The DDX driver changes its behavior depending on the value it reads from

 * i915.enable_fbc, so sanitize it by translating the default value into either

drivers/gpu/drm/i915/display/intel_fbc.h

+3 −0
Original line number Diff line number Diff line
@@ -9,6 +9,7 @@ 
#include <linux/types.h>



enum fb_op_origin;

enum pipe;

struct intel_atomic_state;

struct intel_crtc;

struct intel_crtc_state;
@@ -46,6 +47,8 @@ void intel_fbc_flush(struct intel_display *display, 
		     unsigned int frontbuffer_bits, enum fb_op_origin origin);

void intel_fbc_add_plane(struct intel_fbc *fbc, struct intel_plane *plane);

void intel_fbc_handle_fifo_underrun_irq(struct intel_display *display);

void intel_fbc_read_underrun_dbg_info(struct intel_display *display,

				      enum pipe, bool log);

void intel_fbc_reset_underrun(struct intel_display *display);

void intel_fbc_crtc_debugfs_add(struct intel_crtc *crtc);

void intel_fbc_debugfs_register(struct intel_display *display);

drivers/gpu/drm/i915/display/intel_fbc_regs.h

+2 −0
Original line number Diff line number Diff line
@@ -88,6 +88,8 @@ 
#define DPFC_FENCE_YOFF			_MMIO(0x3218)

#define ILK_DPFC_FENCE_YOFF(fbc_id)	_MMIO_PIPE((fbc_id), 0x43218, 0x43258)

#define DPFC_CHICKEN			_MMIO(0x3224)

#define FBC_DEBUG_STATUS(fbc_id)	_MMIO_PIPE((fbc_id), 0x43220, 0x43260)

#define   FBC_UNDERRUN_DECMPR			REG_BIT(27)

#define ILK_DPFC_CHICKEN(fbc_id)	_MMIO_PIPE((fbc_id), 0x43224, 0x43264)

#define   DPFC_HT_MODIFY			REG_BIT(31) /* pre-ivb */

#define   DPFC_NUKE_ON_ANY_MODIFICATION		REG_BIT(23) /* bdw+ */