Commit dfb77c81 authored by Bjorn Helgaas's avatar Bjorn Helgaas
Browse files

Merge branch 'pci/controller/s32g' 

- Add NXP S32G host controller DT binding and driver (Vincent Guittot)

* pci/controller/s32g:
  MAINTAINERS: Add NXP S32G PCIe controller driver maintainer
  PCI: s32g: Add NXP S32G PCIe controller driver (RC)
  PCI: dwc: Add register and bitfield definitions
  dt-bindings: PCI: s32g: Add NXP S32G PCIe controller
parents c9345412 de45401e

Documentation/devicetree/bindings/pci/nxp,s32g-pcie.yaml

0 → 100644
+130 −0
Original line number Diff line number Diff line 
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)

%YAML 1.2

---

$id: http://devicetree.org/schemas/pci/nxp,s32g-pcie.yaml#

$schema: http://devicetree.org/meta-schemas/core.yaml#



title: NXP S32G2xxx/S32G3xxx PCIe Root Complex controller



maintainers:

  - Bogdan Hamciuc <bogdan.hamciuc@nxp.com>

  - Ionut Vicovan <ionut.vicovan@nxp.com>



description:

  This PCIe controller is based on the Synopsys DesignWare PCIe IP.

  The S32G SoC family has two PCIe controllers, which can be configured as

  either Root Complex or Endpoint.



properties:

  compatible:

    oneOf:

      - enum:

          - nxp,s32g2-pcie

      - items:

          - const: nxp,s32g3-pcie

          - const: nxp,s32g2-pcie



  reg:

    maxItems: 6



  reg-names:

    items:

      - const: dbi

      - const: dbi2

      - const: atu

      - const: dma

      - const: ctrl

      - const: config



  interrupts:

    minItems: 1

    maxItems: 2



  interrupt-names:

    items:

      - const: msi

      - const: dma

    minItems: 1



  pcie@0:

    description:

      Describe the S32G Root Port.

    type: object

    $ref: /schemas/pci/pci-pci-bridge.yaml#



    properties:

      reg:

        maxItems: 1



      phys:

        maxItems: 1



    required:

      - reg

      - phys



    unevaluatedProperties: false



required:

  - compatible

  - reg

  - reg-names

  - interrupts

  - interrupt-names

  - ranges

  - pcie@0



allOf:

  - $ref: /schemas/pci/snps,dw-pcie.yaml#



unevaluatedProperties: false



examples:

  - |

    #include <dt-bindings/interrupt-controller/arm-gic.h>

    #include <dt-bindings/phy/phy.h>



    bus {

        #address-cells = <2>;

        #size-cells = <2>;



        pcie@40400000 {

            compatible = "nxp,s32g3-pcie", "nxp,s32g2-pcie";

            reg = <0x00 0x40400000 0x0 0x00001000>,   /* dbi registers */

                  <0x00 0x40420000 0x0 0x00001000>,   /* dbi2 registers */

                  <0x00 0x40460000 0x0 0x00001000>,   /* atu registers */

                  <0x00 0x40470000 0x0 0x00001000>,   /* dma registers */

                  <0x00 0x40481000 0x0 0x000000f8>,   /* ctrl registers */

                  <0x5f 0xffffe000 0x0 0x00002000>;   /* config space */

            reg-names = "dbi", "dbi2", "atu", "dma", "ctrl", "config";

            dma-coherent;

            #address-cells = <3>;

            #size-cells = <2>;

            device_type = "pci";

            ranges =

                     <0x01000000 0x0 0x00000000 0x5f 0xfffe0000 0x0 0x00010000>,

                     <0x02000000 0x0 0x00000000 0x58 0x00000000 0x0 0x80000000>,

                     <0x02000000 0x1 0x00000000 0x59 0x00000000 0x6 0xfffe0000>;



            bus-range = <0x0 0xff>;

            interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,

                         <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>;

            interrupt-names = "msi", "dma";

            #interrupt-cells = <1>;

            interrupt-map-mask = <0 0 0 0x7>;

            interrupt-map = <0 0 0 1 &gic 0 0 GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>,

                            <0 0 0 2 &gic 0 0 GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>,

                            <0 0 0 3 &gic 0 0 GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>,

                            <0 0 0 4 &gic 0 0 GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>;



            pcie@0 {

                reg = <0x0 0x0 0x0 0x0 0x0>;

                #address-cells = <3>;

                #size-cells = <2>;

                ranges;



                device_type = "pci";

                phys = <&serdes0 PHY_TYPE_PCIE 0 0>;

            };

        };

    };

MAINTAINERS

+9 −0
Original line number Diff line number Diff line
@@ -3132,6 +3132,15 @@ F: arch/arm64/boot/dts/freescale/s32g*.dts* 
F:	drivers/pinctrl/nxp/

F:	drivers/rtc/rtc-s32g.c









ARM/NXP S32G PCIE CONTROLLER DRIVER









M:	Ciprian Marian Costea <ciprianmarian.costea@oss.nxp.com>









R:	NXP S32 Linux Team <s32@nxp.com>









L:	imx@lists.linux.dev









L:	linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)









S:	Maintained









F:	Documentation/devicetree/bindings/pci/nxp,s32g-pcie.yaml









F:	drivers/pci/controller/dwc/pcie-nxp-s32g*

















ARM/NXP S32G/S32R DWMAC ETHERNET DRIVER









M:	Jan Petrous <jan.petrous@oss.nxp.com>









R:	s32@nxp.com
































drivers/pci/controller/dwc/Kconfig



+10
−0






























Original line number
Diff line number
Diff line







@@ -256,6 +256,16 @@ config PCIE_TEGRA194_EP







	  in order to enable device-specific features PCIE_TEGRA194_EP must be









	  selected. This uses the DesignWare core.



















config PCIE_NXP_S32G









	bool "NXP S32G PCIe controller (host mode)"









	depends on ARCH_S32 || COMPILE_TEST









	select PCIE_DW_HOST









	help









	  Enable support for the PCIe controller in NXP S32G based boards to









	  work in Host mode. The controller is based on DesignWare IP and









	  can work either as RC or EP. In order to enable host-specific









	  features PCIE_NXP_S32G must be selected.



















config PCIE_DW_PLAT









	bool










































drivers/pci/controller/dwc/Makefile



+1
−0






























Original line number
Diff line number
Diff line







@@ -10,6 +10,7 @@ obj-$(CONFIG_PCI_DRA7XX) += pci-dra7xx.o







obj-$(CONFIG_PCI_EXYNOS) += pci-exynos.o









obj-$(CONFIG_PCIE_FU740) += pcie-fu740.o









obj-$(CONFIG_PCI_IMX6) += pci-imx6.o









obj-$(CONFIG_PCIE_NXP_S32G) += pcie-nxp-s32g.o









obj-$(CONFIG_PCIE_SPEAR13XX) += pcie-spear13xx.o









# ARM32 platforms use hook_fault_code() and cannot support loadable module.









obj-$(CONFIG_PCI_KEYSTONE) += pci-keystone.o
































drivers/pci/controller/dwc/pcie-designware.h



+8
−0






























Original line number
Diff line number
Diff line







@@ -121,6 +121,7 @@

















#define GEN3_RELATED_OFF			0x890









#define GEN3_RELATED_OFF_GEN3_ZRXDC_NONCOMPL	BIT(0)









#define GEN3_RELATED_OFF_EQ_PHASE_2_3		BIT(9)









#define GEN3_RELATED_OFF_RXEQ_RGRDLESS_RXTS	BIT(13)









#define GEN3_RELATED_OFF_GEN3_EQ_DISABLE	BIT(16)









#define GEN3_RELATED_OFF_RATE_SHADOW_SEL_SHIFT	24








@@ -138,6 +139,13 @@







#define GEN3_EQ_FMDC_MAX_PRE_CURSOR_DELTA	GENMASK(13, 10)









#define GEN3_EQ_FMDC_MAX_POST_CURSOR_DELTA	GENMASK(17, 14)



















#define COHERENCY_CONTROL_1_OFF			0x8E0









#define CFG_MEMTYPE_BOUNDARY_LOW_ADDR_MASK	GENMASK(31, 2)









#define CFG_MEMTYPE_VALUE			BIT(0)



















#define COHERENCY_CONTROL_2_OFF			0x8E4









#define COHERENCY_CONTROL_3_OFF			0x8E8



















#define PCIE_PORT_MULTI_LANE_CTRL	0x8C0









#define PORT_MLTI_UPCFG_SUPPORT		BIT(7)