Commit dfc83cc8 authored by Ian Rogers's avatar Ian Rogers Committed by Namhyung Kim
Browse files

perf vendor events intel: Update meteorlake to 1.03 

1.03 events were released in:
https://github.com/intel/perfmon/commit/501a29e88b57e8b01d610168d0101d6181b15e28


It added a lot of events and all uncore events.

Signed-off-by: default avatarIan Rogers <irogers@google.com>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: Eduard Zingerman <eddyz87@gmail.com>
Cc: Sohom Datta <sohomdatta1@gmail.com>
Cc: Peter Zijlstra <peterz@infradead.org>
Cc: Adrian Hunter <adrian.hunter@intel.com>
Cc: Caleb Biggers <caleb.biggers@intel.com>
Cc: Edward Baker <edward.baker@intel.com>
Cc: Perry Taylor <perry.taylor@intel.com>
Cc: Samantha Alt <samantha.alt@intel.com>
Cc: Weilin Wang <weilin.wang@intel.com>
Cc: Arnaldo Carvalho de Melo <acme@kernel.org>
Cc: Andrii Nakryiko <andrii@kernel.org>
Cc: Jiri Olsa <jolsa@kernel.org>
Cc: Namhyung Kim <namhyung@kernel.org>
Cc: Jing Zhang <renyu.zj@linux.alibaba.com>
Cc: Kajol Jain <kjain@linux.ibm.com>
Cc: Alexander Shishkin <alexander.shishkin@linux.intel.com>
Cc: Kan Liang <kan.liang@linux.intel.com>
Cc: Zhengjun Xing <zhengjun.xing@linux.intel.com>
Cc: John Garry <john.g.garry@oracle.com>
Cc: Ingo Molnar <mingo@redhat.com>
Link: https://lore.kernel.org/r/20230623151016.4193660-6-irogers@google.com


Signed-off-by: default avatarNamhyung Kim <namhyung@kernel.org>
parent 7e74ece3

tools/perf/pmu-events/arch/x86/mapfile.csv

+1 −1
Original line number Diff line number Diff line
@@ -19,7 +19,7 @@ GenuineIntel-6-3A,v24,ivybridge,core 
GenuineIntel-6-3E,v23,ivytown,core

GenuineIntel-6-2D,v23,jaketown,core

GenuineIntel-6-(57|85),v10,knightslanding,core

GenuineIntel-6-A[AC],v1.01,meteorlake,core

GenuineIntel-6-A[AC],v1.03,meteorlake,core

GenuineIntel-6-1[AEF],v3,nehalemep,core

GenuineIntel-6-2E,v3,nehalemex,core

GenuineIntel-6-A7,v1.01,rocketlake,core

tools/perf/pmu-events/arch/x86/meteorlake/cache.json

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tools/perf/pmu-events/arch/x86/meteorlake/floating-point.json

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[

    {

        "BriefDescription": "This event counts the cycles the floating point divider is busy.",

        "CounterMask": "1",

        "EventCode": "0xb0",

        "EventName": "ARITH.FPDIV_ACTIVE",

        "SampleAfterValue": "1000003",

        "UMask": "0x1",

        "Unit": "cpu_core"

    },

    {

        "BriefDescription": "Counts all microcode FP assists.",

        "EventCode": "0xc1",

        "EventName": "ASSISTS.FP",

        "PublicDescription": "Counts all microcode Floating Point assists.",

        "SampleAfterValue": "100003",

        "UMask": "0x2",

        "Unit": "cpu_core"

    },

    {

        "BriefDescription": "ASSISTS.SSE_AVX_MIX",

        "EventCode": "0xc1",

        "EventName": "ASSISTS.SSE_AVX_MIX",

        "SampleAfterValue": "1000003",

        "UMask": "0x10",

        "Unit": "cpu_core"

    },

    {

        "BriefDescription": "FP_ARITH_DISPATCHED.PORT_0",

        "EventCode": "0xb3",

        "EventName": "FP_ARITH_DISPATCHED.PORT_0",

        "SampleAfterValue": "2000003",

        "UMask": "0x1",

        "Unit": "cpu_core"

    },

    {

        "BriefDescription": "FP_ARITH_DISPATCHED.PORT_1",

        "EventCode": "0xb3",

        "EventName": "FP_ARITH_DISPATCHED.PORT_1",

        "SampleAfterValue": "2000003",

        "UMask": "0x2",

        "Unit": "cpu_core"

    },

    {

        "BriefDescription": "Counts number of SSE/AVX computational 128-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below.  Each count represents 2 computation operations, one for each element.  Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT DPP FM(N)ADD/SUB.  DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.",

        "EventCode": "0xc7",

        "EventName": "FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE",

        "PublicDescription": "Number of SSE/AVX computational 128-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below.  Each count represents 2 computation operations, one for each element.  Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT DPP FM(N)ADD/SUB.  DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.",

        "SampleAfterValue": "100003",

        "UMask": "0x4",

        "Unit": "cpu_core"

    },

    {

        "BriefDescription": "Number of SSE/AVX computational 128-bit packed single precision floating-point instructions retired; some instructions will count twice as noted below.  Each count represents 4 computation operations, one for each element.  Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB MUL DIV MIN MAX RCP14 RSQRT14 SQRT DPP FM(N)ADD/SUB.  DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.",

        "EventCode": "0xc7",

        "EventName": "FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE",

        "PublicDescription": "Number of SSE/AVX computational 128-bit packed single precision floating-point instructions retired; some instructions will count twice as noted below.  Each count represents 4 computation operations, one for each element.  Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT RSQRT RCP DPP FM(N)ADD/SUB.  DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.",

        "SampleAfterValue": "100003",

        "UMask": "0x8",

        "Unit": "cpu_core"

    },

    {

        "BriefDescription": "Counts number of SSE/AVX computational 256-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below.  Each count represents 4 computation operations, one for each element.  Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT FM(N)ADD/SUB.  FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.",

        "EventCode": "0xc7",

        "EventName": "FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE",

        "PublicDescription": "Number of SSE/AVX computational 256-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below.  Each count represents 4 computation operations, one for each element.  Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT FM(N)ADD/SUB.  FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.",

        "SampleAfterValue": "100003",

        "UMask": "0x10",

        "Unit": "cpu_core"

    },

    {

        "BriefDescription": "Counts number of SSE/AVX computational 256-bit packed single precision floating-point instructions retired; some instructions will count twice as noted below.  Each count represents 8 computation operations, one for each element.  Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT RSQRT RCP DPP FM(N)ADD/SUB.  DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.",

        "EventCode": "0xc7",

        "EventName": "FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE",

        "PublicDescription": "Number of SSE/AVX computational 256-bit packed single precision floating-point instructions retired; some instructions will count twice as noted below.  Each count represents 8 computation operations, one for each element.  Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT RSQRT RCP DPP FM(N)ADD/SUB.  DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.",

        "SampleAfterValue": "100003",

        "UMask": "0x20",

        "Unit": "cpu_core"

    },

    {

        "BriefDescription": "Number of SSE/AVX computational 128-bit packed single and 256-bit packed double precision FP instructions retired; some instructions will count twice as noted below.  Each count represents 2 or/and 4 computation operations, 1 for each element.  Applies to SSE* and AVX* packed single precision and packed double precision FP instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX RCP14 RSQRT14 SQRT DPP FM(N)ADD/SUB.  DPP and FM(N)ADD/SUB count twice as they perform 2 calculations per element.",

        "EventCode": "0xc7",

        "EventName": "FP_ARITH_INST_RETIRED.4_FLOPS",

        "PublicDescription": "Number of SSE/AVX computational 128-bit packed single precision and 256-bit packed double precision  floating-point instructions retired; some instructions will count twice as noted below.  Each count represents 2 or/and 4 computation operations, one for each element.  Applies to SSE* and AVX* packed single precision floating-point and packed double precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX RCP14 RSQRT14 SQRT DPP FM(N)ADD/SUB.  DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.",

        "SampleAfterValue": "100003",

        "UMask": "0x18",

        "Unit": "cpu_core"

    },

    {

        "BriefDescription": "Number of SSE/AVX computational scalar floating-point instructions retired; some instructions will count twice as noted below.  Applies to SSE* and AVX* scalar, double and single precision floating-point: ADD SUB MUL DIV MIN MAX RCP14 RSQRT14 RANGE SQRT DPP FM(N)ADD/SUB.  DPP and FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element.",

        "EventCode": "0xc7",

        "EventName": "FP_ARITH_INST_RETIRED.SCALAR",

        "PublicDescription": "Number of SSE/AVX computational scalar single precision and double precision floating-point instructions retired; some instructions will count twice as noted below.  Each count represents 1 computational operation. Applies to SSE* and AVX* scalar single precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT RSQRT RCP FM(N)ADD/SUB.  FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.",

        "SampleAfterValue": "1000003",

        "UMask": "0x3",

        "Unit": "cpu_core"

    },

    {

        "BriefDescription": "Counts number of SSE/AVX computational scalar double precision floating-point instructions retired; some instructions will count twice as noted below.  Each count represents 1 computational operation. Applies to SSE* and AVX* scalar double precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT FM(N)ADD/SUB.  FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.",

        "EventCode": "0xc7",

        "EventName": "FP_ARITH_INST_RETIRED.SCALAR_DOUBLE",

        "PublicDescription": "Number of SSE/AVX computational scalar double precision floating-point instructions retired; some instructions will count twice as noted below.  Each count represents 1 computational operation. Applies to SSE* and AVX* scalar double precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT FM(N)ADD/SUB.  FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.",

        "SampleAfterValue": "100003",

        "UMask": "0x1",

        "Unit": "cpu_core"

    },

    {

        "BriefDescription": "Counts number of SSE/AVX computational scalar single precision floating-point instructions retired; some instructions will count twice as noted below.  Each count represents 1 computational operation. Applies to SSE* and AVX* scalar single precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT RSQRT RCP FM(N)ADD/SUB.  FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.",

        "EventCode": "0xc7",

        "EventName": "FP_ARITH_INST_RETIRED.SCALAR_SINGLE",

        "PublicDescription": "Number of SSE/AVX computational scalar single precision floating-point instructions retired; some instructions will count twice as noted below.  Each count represents 1 computational operation. Applies to SSE* and AVX* scalar single precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT RSQRT RCP FM(N)ADD/SUB.  FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.",

        "SampleAfterValue": "100003",

        "UMask": "0x2",

        "Unit": "cpu_core"

    },

    {

        "BriefDescription": "Number of any Vector retired FP arithmetic instructions",

        "EventCode": "0xc7",

        "EventName": "FP_ARITH_INST_RETIRED.VECTOR",

        "PublicDescription": "Number of any Vector retired FP arithmetic instructions.  The DAZ and FTZ flags in the MXCSR register need to be set when using these events.",

        "SampleAfterValue": "1000003",

        "UMask": "0xfc",

        "Unit": "cpu_core"

    },

    {

        "BriefDescription": "Counts the number of floating point operations retired that required microcode assist.",

        "EventCode": "0xc3",

        "EventName": "MACHINE_CLEARS.FP_ASSIST",

        "PublicDescription": "Counts the number of floating point operations retired that required microcode assist, which is not a reflection of the number of FP operations, instructions or uops.",

        "SampleAfterValue": "20003",

        "UMask": "0x4",

        "Unit": "cpu_atom"

    },

    {

        "BriefDescription": "Counts the number of floating point divide uops retired (x87 and sse, including x87 sqrt).",

        "EventCode": "0xc2",

        "EventName": "UOPS_RETIRED.FPDIV",

        "PEBS": "1",

        "SampleAfterValue": "2000003",

        "UMask": "0x8",

        "Unit": "cpu_atom"

    }

]

tools/perf/pmu-events/arch/x86/meteorlake/frontend.json

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tools/perf/pmu-events/arch/x86/meteorlake/memory.json

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Original line number Diff line number Diff line 
[

    {

        "BriefDescription": "Cycles while L3 cache miss demand load is outstanding.",

        "CounterMask": "2",

        "EventCode": "0xa3",

        "EventName": "CYCLE_ACTIVITY.CYCLES_L3_MISS",

        "SampleAfterValue": "1000003",

        "UMask": "0x2",

        "Unit": "cpu_core"

    },

    {

        "BriefDescription": "Execution stalls while L3 cache miss demand load is outstanding.",

        "CounterMask": "6",

        "EventCode": "0xa3",

        "EventName": "CYCLE_ACTIVITY.STALLS_L3_MISS",

        "SampleAfterValue": "1000003",

        "UMask": "0x6",

        "Unit": "cpu_core"

    },

    {

        "BriefDescription": "Counts the number of cycles that the head (oldest load) of the load buffer is stalled due to any number of reasons, including an L1 miss, WCB full, pagewalk, store address block or store data block, on a load that retires.",

        "EventCode": "0x05",

        "EventName": "LD_HEAD.ANY_AT_RET",

        "SampleAfterValue": "1000003",

        "UMask": "0xff",

        "Unit": "cpu_atom"

    },

    {

        "BriefDescription": "Counts the number of cycles that the head (oldest load) of the load buffer is stalled due to a core bound stall including a store address match, a DTLB miss or a page walk that detains the load from retiring.",

        "EventCode": "0x05",

        "EventName": "LD_HEAD.L1_BOUND_AT_RET",

        "SampleAfterValue": "1000003",

        "UMask": "0xf4",

        "Unit": "cpu_atom"

    },

    {

        "BriefDescription": "Counts the number of cycles that the head (oldest load) of the load buffer and retirement are both stalled due to a DL1 miss.",

        "EventCode": "0x05",

        "EventName": "LD_HEAD.L1_MISS_AT_RET",

        "SampleAfterValue": "1000003",

        "UMask": "0x81",

        "Unit": "cpu_atom"

    },

    {

        "BriefDescription": "Counts the number of cycles that the head (oldest load) of the load buffer and retirement are both stalled due to other block cases.",

        "EventCode": "0x05",

        "EventName": "LD_HEAD.OTHER_AT_RET",

        "PublicDescription": "Counts the number of cycles that the head (oldest load) of the load buffer and retirement are both stalled due to other block cases such as pipeline conflicts, fences, etc.",

        "SampleAfterValue": "1000003",

        "UMask": "0xc0",

        "Unit": "cpu_atom"

    },

    {

        "BriefDescription": "Counts the number of cycles that the head (oldest load) of the load buffer and retirement are both stalled due to a pagewalk.",

        "EventCode": "0x05",

        "EventName": "LD_HEAD.PGWALK_AT_RET",

        "SampleAfterValue": "1000003",

        "UMask": "0xa0",

        "Unit": "cpu_atom"

    },

    {

        "BriefDescription": "Counts the number of cycles that the head (oldest load) of the load buffer and retirement are both stalled due to a store address match.",

        "EventCode": "0x05",

        "EventName": "LD_HEAD.ST_ADDR_AT_RET",

        "SampleAfterValue": "1000003",

        "UMask": "0x84",

        "Unit": "cpu_atom"

    },

    {

        "BriefDescription": "Execution stalls while L1 cache miss demand load is outstanding.",

        "CounterMask": "3",

        "EventCode": "0x47",

        "EventName": "MEMORY_ACTIVITY.STALLS_L1D_MISS",

        "SampleAfterValue": "1000003",

        "UMask": "0x3",

        "Unit": "cpu_core"

    },

    {

        "BriefDescription": "Execution stalls while L2 cache miss demand cacheable load request is outstanding.",

        "CounterMask": "5",

        "EventCode": "0x47",

        "EventName": "MEMORY_ACTIVITY.STALLS_L2_MISS",

        "PublicDescription": "Execution stalls while L2 cache miss demand cacheable load request is outstanding (will not count for uncacheable demand requests e.g. bus lock).",

        "SampleAfterValue": "1000003",

        "UMask": "0x5",

        "Unit": "cpu_core"

    },

    {

        "BriefDescription": "Execution stalls while L3 cache miss demand cacheable load request is outstanding.",

        "CounterMask": "9",

        "EventCode": "0x47",

        "EventName": "MEMORY_ACTIVITY.STALLS_L3_MISS",

        "PublicDescription": "Execution stalls while L3 cache miss demand cacheable load request is outstanding (will not count for uncacheable demand requests e.g. bus lock).",

        "SampleAfterValue": "1000003",

        "UMask": "0x9",

        "Unit": "cpu_core"

    },

    {

        "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 128 cycles.",

        "Data_LA": "1",
@@ -115,43 +211,29 @@ 
        "Unit": "cpu_core"

    },

    {

        "BriefDescription": "Counts demand data reads that were not supplied by the L3 cache.",

        "EventCode": "0xB7",

        "EventName": "OCR.DEMAND_DATA_RD.L3_MISS",

        "MSRIndex": "0x1a6,0x1a7",

        "MSRValue": "0x3FBFC00001",

        "SampleAfterValue": "100003",

        "UMask": "0x1",

        "BriefDescription": "Counts misaligned loads that are 4K page splits.",

        "EventCode": "0x13",

        "EventName": "MISALIGN_MEM_REF.LOAD_PAGE_SPLIT",

        "PEBS": "1",

        "SampleAfterValue": "200003",

        "UMask": "0x2",

        "Unit": "cpu_atom"

    },

    {

        "BriefDescription": "Counts demand data reads that were not supplied by the L3 cache.",

        "EventCode": "0x2A,0x2B",

        "EventName": "OCR.DEMAND_DATA_RD.L3_MISS",

        "MSRIndex": "0x1a6,0x1a7",

        "MSRValue": "0x3FBFC00001",

        "SampleAfterValue": "100003",

        "UMask": "0x1",

        "Unit": "cpu_core"

    },

    {

        "BriefDescription": "Counts demand reads for ownership (RFO) and software prefetches for exclusive ownership (PREFETCHW) that were not supplied by the L3 cache.",

        "EventCode": "0xB7",

        "EventName": "OCR.DEMAND_RFO.L3_MISS",

        "MSRIndex": "0x1a6,0x1a7",

        "MSRValue": "0x3FBFC00002",

        "SampleAfterValue": "100003",

        "UMask": "0x1",

        "BriefDescription": "Counts misaligned stores that are 4K page splits.",

        "EventCode": "0x13",

        "EventName": "MISALIGN_MEM_REF.STORE_PAGE_SPLIT",

        "PEBS": "1",

        "SampleAfterValue": "200003",

        "UMask": "0x4",

        "Unit": "cpu_atom"

    },

    {

        "BriefDescription": "Counts demand read for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that were not supplied by the L3 cache.",

        "EventCode": "0x2A,0x2B",

        "EventName": "OCR.DEMAND_RFO.L3_MISS",

        "MSRIndex": "0x1a6,0x1a7",

        "MSRValue": "0x3FBFC00002",

        "BriefDescription": "Counts demand data read requests that miss the L3 cache.",

        "EventCode": "0x21",

        "EventName": "OFFCORE_REQUESTS.L3_MISS_DEMAND_DATA_RD",

        "SampleAfterValue": "100003",

        "UMask": "0x1",

        "UMask": "0x10",

        "Unit": "cpu_core"

    }

]