Unverified Commit dfdded9b authored by Arnd Bergmann's avatar Arnd Bergmann
Browse files

Merge tag 'qcom-dts-for-5.17' of... 

Merge tag 'qcom-dts-for-5.17' of git://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux into arm/dt

Qualcomm DeviceTree updates for v5.17

To SDX55 this introduces the description of the IPA, PCIe PHY and PCIe
endpoint controller, as well as enables these for the FN960 device.

The SDX65 5G platform is introduced, currently with definitions
necessary to boot to a shell.

The undocumented property "input-name" is dropped throughout the dts
files, dwc3 nodes throughout gains more specific compatibles and lastly
building of the Dragonboard 410c DTB on ARM32 is enabled, in addition to
its normal operation in 64-bit mode.

* tag 'qcom-dts-for-5.17' of git://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux:
  ARM: dts: qcom: Drop input-name property
  ARM: dts: qcom: sdx65: Add pincontrol node
  ARM: dts: qcom: Add SDX65 platform and MTP board support
  dt-bindings: arm: qcom: Document SDX65 platform and boards
  dt-bindings: clock: Add SDX65 GCC clock bindings
  ARM: dts: qcom: Build apq8016-sbc/DragonBoard 410c DTB on ARM32
  ARM: dts: qcom: sdx55-t55: Enable IPA
  ARM: dts: qcom: sdx55-fn980: Enable IPA
  ARM: dts: qcom: sdx55-fn980: Enable PCIe EP
  ARM: dts: qcom: sdx55: Add support for PCIe EP
  ARM: dts: qcom: sdx55-fn980: Enable PCIE0 PHY
  ARM: dts: qcom: sdx55: Add support for PCIe PHY
  ARM: dts: qcom: update USB nodes with new platform specific compatible

Link: https://lore.kernel.org/r/20211221042154.3621955-1-bjorn.andersson@linaro.org


Signed-off-by: default avatarArnd Bergmann <arnd@arndb.de>
parents 5c4a5b36 ef5ad260

Documentation/devicetree/bindings/arm/qcom.yaml

+6 −0
Original line number Diff line number Diff line
@@ -48,6 +48,7 @@ description: | 
        sdx65

        sm7225

        sm8150

        sdx65

        sm8250

        sm8350
@@ -224,6 +225,11 @@ properties: 
              - qcom,sdx65-mtp

          - const: qcom,sdx65



      - items:

          - enum:

              - qcom,sdx65-mtp

          - const: qcom,sdx65



      - items:

          - enum:

              - qcom,ipq6018-cp01

Documentation/devicetree/bindings/clock/qcom,gcc-sdx65.yaml

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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)

%YAML 1.2

---

$id: http://devicetree.org/schemas/clock/qcom,gcc-sdx65.yaml#

$schema: http://devicetree.org/meta-schemas/core.yaml#



title: Qualcomm Global Clock & Reset Controller Binding for SDX65



maintainers:

  - Vamsi krishna Lanka <quic_vamslank@quicinc.com>



description: |

  Qualcomm global clock control module which supports the clocks, resets and

  power domains on SDX65



  See also:

  - dt-bindings/clock/qcom,gcc-sdx65.h



properties:

  compatible:

    const: qcom,gcc-sdx65



  reg:

    maxItems: 1



  clocks:

    items:

      - description: Board XO source

      - description: Board active XO source

      - description: Sleep clock source

      - description: PCIE Pipe clock source

      - description: USB3 phy wrapper pipe clock source

      - description: PLL test clock source (Optional clock)

    minItems: 5



  clock-names:

    items:

      - const: bi_tcxo

      - const: bi_tcxo_ao

      - const: sleep_clk

      - const: pcie_pipe_clk

      - const: usb3_phy_wrapper_gcc_usb30_pipe_clk

      - const: core_bi_pll_test_se # Optional clock

    minItems: 5



  '#clock-cells':

    const: 1



  '#reset-cells':

    const: 1



  '#power-domain-cells':

    const: 1



required:

  - compatible

  - reg

  - clocks

  - clock-names

  - '#clock-cells'

  - '#reset-cells'

  - '#power-domain-cells'



additionalProperties: false



examples:

  - |

    #include <dt-bindings/clock/qcom,rpmh.h>

    clock-controller@100000 {

      compatible = "qcom,gcc-sdx65";

      reg = <0x100000 0x1f7400>;

      clocks = <&rpmhcc RPMH_CXO_CLK>, <&rpmhcc RPMH_CXO_CLK_A>, <&sleep_clk>,

               <&pcie_pipe_clk>, <&usb3_phy_wrapper_gcc_usb30_pipe_clk>, <&pll_test_clk>;

      clock-names = "bi_tcxo", "bi_tcxo_ao", "sleep_clk",

                    "pcie_pipe_clk", "usb3_phy_wrapper_gcc_usb30_pipe_clk", "core_bi_pll_test_se";

      #clock-cells = <1>;

      #reset-cells = <1>;

      #power-domain-cells = <1>;

    };

...

arch/arm/boot/dts/Makefile

+3 −1
Original line number Diff line number Diff line
@@ -966,6 +966,7 @@ dtb-$(CONFIG_ARCH_OXNAS) += \ 
	ox810se-wd-mbwe.dtb \

	ox820-cloudengines-pogoplug-series-3.dtb

dtb-$(CONFIG_ARCH_QCOM) += \

	qcom-apq8016-sbc.dtb \

	qcom-apq8026-lg-lenok.dtb \

	qcom-apq8060-dragonboard.dtb \

	qcom-apq8064-cm-qs600.dtb \
@@ -998,7 +999,8 @@ dtb-$(CONFIG_ARCH_QCOM) += \ 
	qcom-mdm9615-wp8548-mangoh-green.dtb \

	qcom-sdx55-mtp.dtb \

	qcom-sdx55-t55.dtb \

	qcom-sdx55-telit-fn980-tlb.dtb

	qcom-sdx55-telit-fn980-tlb.dtb \

	qcom-sdx65-mtp.dtb

dtb-$(CONFIG_ARCH_RDA) += \

	rda8810pl-orangepi-2g-iot.dtb \

	rda8810pl-orangepi-i96.dtb

arch/arm/boot/dts/qcom-apq8016-sbc.dts

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// SPDX-License-Identifier: GPL-2.0-only

#include "arm64/qcom/apq8016-sbc.dts"

arch/arm/boot/dts/qcom-apq8064-sony-xperia-yuga.dts

+0 −1
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@@ -19,7 +19,6 @@ chosen { 


	gpio-keys {

		compatible = "gpio-keys";

		input-name = "gpio-keys";



		pinctrl-names = "default";

		pinctrl-0 = <&gpio_keys_pin_a>;