Commit dff68b2f authored by Taniya Das's avatar Taniya Das Committed by Bjorn Andersson
Browse files

clk: qcom: gpucc-sa8775p: Park RCG's clk source at XO during disable 



The RCG's clk src has to be parked at XO while disabling as per the
HW recommendation, hence use clk_rcg2_shared_ops to achieve the same.
Also gpu_cc_cb_clk is recommended to be kept always ON, hence use
clk_branch2_aon_ops to keep the clock always ON.

Fixes: 0afa16af ("clk: qcom: add the GPUCC driver for sa8775p")
Signed-off-by: default avatarTaniya Das <quic_tdas@quicinc.com>
Reviewed-by: default avatarKonrad Dybcio <konrad.dybcio@linaro.org>
Link: https://lore.kernel.org/r/20240612-sa8775p-v2-gcc-gpucc-fixes-v2-5-adcc756a23df@quicinc.com


Signed-off-by: default avatarBjorn Andersson <andersson@kernel.org>
parent e69386d4

drivers/clk/qcom/gpucc-sa8775p.c

+4 −4
Original line number Diff line number Diff line
@@ -161,7 +161,7 @@ static struct clk_rcg2 gpu_cc_ff_clk_src = { 
		.name = "gpu_cc_ff_clk_src",

		.parent_data = gpu_cc_parent_data_0,

		.num_parents = ARRAY_SIZE(gpu_cc_parent_data_0),

		.ops = &clk_rcg2_ops,

		.ops = &clk_rcg2_shared_ops,

	},

};
@@ -181,7 +181,7 @@ static struct clk_rcg2 gpu_cc_gmu_clk_src = { 
		.parent_data = gpu_cc_parent_data_1,

		.num_parents = ARRAY_SIZE(gpu_cc_parent_data_1),

		.flags = CLK_SET_RATE_PARENT,

		.ops = &clk_rcg2_ops,

		.ops = &clk_rcg2_shared_ops,

	},

};
@@ -200,7 +200,7 @@ static struct clk_rcg2 gpu_cc_hub_clk_src = { 
		.name = "gpu_cc_hub_clk_src",

		.parent_data = gpu_cc_parent_data_2,

		.num_parents = ARRAY_SIZE(gpu_cc_parent_data_2),

		.ops = &clk_rcg2_ops,

		.ops = &clk_rcg2_shared_ops,

	},

};
@@ -294,7 +294,7 @@ static struct clk_branch gpu_cc_cb_clk = { 
		.enable_mask = BIT(0),

		.hw.init = &(const struct clk_init_data){

			.name = "gpu_cc_cb_clk",

			.ops = &clk_branch2_ops,

			.ops = &clk_branch2_aon_ops,

		},

	},

};