Commit dffaa1be authored by Clément Le Goffic's avatar Clément Le Goffic Committed by Krzysztof Kozlowski
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dt-bindings: memory: factorise LPDDR props into SDRAM props 



LPDDR and DDR bindings are SDRAM types and are likely to share the same
properties (at least for density, io-width and reg).
To avoid bindings duplication, factorise the properties.

The compatible description has been updated because the MR (Mode
registers) used to get manufacturer ID and revision ID are not present
in case of DDR.
Those information should be in a SPD (Serial Presence Detect) EEPROM in
case of DIMM module or are known in case of soldered memory chips as
they are in the datasheet of the memory chips.

Signed-off-by: default avatarClément Le Goffic <clement.legoffic@foss.st.com>
Reviewed-by: default avatarKrzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: default avatarClément Le Goffic <legoffic.clement@gmail.com>
Link: https://patch.msgid.link/20251118-b4-ddr-bindings-v9-1-a033ac5144da@gmail.com


Signed-off-by: default avatarKrzysztof Kozlowski <krzk@kernel.org>
parent 78da7027

Documentation/devicetree/bindings/memory-controllers/ddr/jedec,lpddr2.yaml

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@@ -10,7 +10,7 @@ maintainers: 
  - Krzysztof Kozlowski <krzk@kernel.org>



allOf:

  - $ref: jedec,lpddr-props.yaml#

  - $ref: jedec,sdram-props.yaml#



properties:

  compatible:

Documentation/devicetree/bindings/memory-controllers/ddr/jedec,lpddr3.yaml

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@@ -10,7 +10,7 @@ maintainers: 
  - Krzysztof Kozlowski <krzk@kernel.org>



allOf:

  - $ref: jedec,lpddr-props.yaml#

  - $ref: jedec,sdram-props.yaml#



properties:

  compatible:

Documentation/devicetree/bindings/memory-controllers/ddr/jedec,lpddr4.yaml

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@@ -10,7 +10,7 @@ maintainers: 
  - Krzysztof Kozlowski <krzk@kernel.org>



allOf:

  - $ref: jedec,lpddr-props.yaml#

  - $ref: jedec,sdram-props.yaml#



properties:

  compatible:

Documentation/devicetree/bindings/memory-controllers/ddr/jedec,lpddr5.yaml

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@@ -10,7 +10,7 @@ maintainers: 
  - Krzysztof Kozlowski <krzk@kernel.org>



allOf:

  - $ref: jedec,lpddr-props.yaml#

  - $ref: jedec,sdram-props.yaml#



properties:

  compatible:

Documentation/devicetree/bindings/memory-controllers/ddr/jedec,lpddr-props.yaml→Documentation/devicetree/bindings/memory-controllers/ddr/jedec,sdram-props.yaml

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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)

%YAML 1.2

---

$id: http://devicetree.org/schemas/memory-controllers/ddr/jedec,lpddr-props.yaml#

$id: http://devicetree.org/schemas/memory-controllers/ddr/jedec,sdram-props.yaml#

$schema: http://devicetree.org/meta-schemas/core.yaml#



title: Common properties for LPDDR types

title: Common properties for SDRAM types



description:

  Different LPDDR types generally use the same properties and only differ in the

  Different SDRAM types generally use the same properties and only differ in the

  range of legal values for each. This file defines the common parts that can be

  reused for each type. Nodes using this schema should generally be nested under

  an LPDDR channel node.

  a SDRAM channel node.



maintainers:

  - Krzysztof Kozlowski <krzk@kernel.org>



properties:

  compatible:

    description:

    description: |

      Compatible strings can be either explicit vendor names and part numbers

      (e.g. elpida,ECB240ABACN), or generated strings of the form

      lpddrX-YY,ZZZZ where X is the LPDDR version, YY is the manufacturer ID

      (from MR5) and ZZZZ is the revision ID (from MR6 and MR7). Both IDs are

      formatted in lower case hexadecimal representation with leading zeroes.

      The latter form can be useful when LPDDR nodes are created at runtime by

      boot firmware that doesn't have access to static part number information.

      lpddrX-YY,ZZZZ or ddrX-YYYY,AAAA...-ZZ where X, Y, and Z are lowercase

      hexadecimal with leading zeroes, and A is lowercase ASCII.

      For LPDDR and DDR SDRAM, X is the SDRAM version (2, 3, 4, etc.).

      For LPDDR SDRAM:

        - YY is the manufacturer ID (from MR5), 1 byte

        - ZZZZ is the revision ID (from MR6 and MR7), 2 bytes

      For DDR4 SDRAM with SPD, according to JEDEC SPD4.1.2.L-6:

        - YYYY is the manufacturer ID, 2 bytes, from bytes 320 and 321

        - AAAA... is the part number, 20 bytes (20 chars) from bytes 329 to 348

          without trailing spaces

        - ZZ is the revision ID, 1 byte, from byte 349

      The former form is useful when the SDRAM vendor and part number are

      known, for example, when memory is soldered on the board. The latter

      form is useful when SDRAM nodes are created at runtime by boot firmware

      that doesn't have access to static part number information.



  reg:

    description:

      The rank number of this LPDDR rank when used as a subnode to an LPDDR

      The rank number of this memory rank when used as a subnode to an memory

      channel.

    minimum: 0

    maximum: 3



  revision-id:

    $ref: /schemas/types.yaml#/definitions/uint32-array

    description:

      Revision IDs read from Mode Register 6 and 7. One byte per uint32 cell (i.e. <MR6 MR7>).

    description: |

      SDRAM revision ID:

        - LPDDR SDRAM, decoded from Mode Registers 6 and 7, always 2 bytes.

        - DDR4 SDRAM, decoded from the SPD from byte 349 according to

          JEDEC SPD4.1.2.L-6, always 1 byte.

      One byte per uint32 cell (e.g., <MR6 MR7>).

    maxItems: 2

    items:

      minimum: 0
@@ -44,8 +58,11 @@ properties: 


  density:

    $ref: /schemas/types.yaml#/definitions/uint32

    description:

      Density in megabits of SDRAM chip. Decoded from Mode Register 8.

    description: |

      Density of the SDRAM chip in megabits:

        - LPDDR SDRAM, decoded from Mode Register 8.

        - DDR4 SDRAM, decoded from the SPD from bits 3-0 of byte 4 according to

          JEDEC SPD4.1.2.L-6.

    enum:

      - 64

      - 128
@@ -64,8 +81,11 @@ properties: 


  io-width:

    $ref: /schemas/types.yaml#/definitions/uint32

    description:

      IO bus width in bits of SDRAM chip. Decoded from Mode Register 8.

    description: |

      I/O bus width in bits of the SDRAM chip:

        - LPDDR SDRAM, decoded from Mode Register 8.

        - DDR4 SDRAM, decoded from the SPD from bits 2-0 of byte 12 according to

          JEDEC SPD4.1.2.L-6.

    enum:

      - 8

      - 16