Unverified Commit e010c049 authored by Tudor Ambarus's avatar Tudor Ambarus Committed by Mark Brown
Browse files

spi: s3c64xx: add support for google,gs101-spi 



Add support for GS101 SPI. GS101 integrates 16 SPI nodes, all with 64
bytes FIFOs. GS101 allows just 32 bit register accesses, otherwise a
Serror Interrupt is raised. Do the write reg accesses in 32 bits.

Reviewed-by: default avatarSam Protsenko <semen.protsenko@linaro.org>
Signed-off-by: default avatarTudor Ambarus <tudor.ambarus@linaro.org>
Link: https://lore.kernel.org/r/20240207111516.2563218-5-tudor.ambarus@linaro.org


Signed-off-by: default avatarMark Brown <broonie@kernel.org>
parent b7bafb9f

drivers/spi/spi-s3c64xx.c

+17 −1
Original line number Diff line number Diff line
@@ -17,7 +17,7 @@ 


#include <linux/platform_data/spi-s3c64xx.h>



#define MAX_SPI_PORTS		12

#define MAX_SPI_PORTS		16

#define S3C64XX_SPI_QUIRK_CS_AUTO	(1 << 1)

#define AUTOSUSPEND_TIMEOUT	2000
@@ -1534,6 +1534,19 @@ static const struct s3c64xx_spi_port_config fsd_spi_port_config = { 
	.quirks		= S3C64XX_SPI_QUIRK_CS_AUTO,

};



static const struct s3c64xx_spi_port_config gs101_spi_port_config = {

	.fifo_lvl_mask	= { 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f,

			    0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f},

	.rx_lvl_offset	= 15,

	.tx_st_done	= 25,

	.clk_div	= 4,

	.high_speed	= true,

	.clk_from_cmu	= true,

	.has_loopback	= true,

	.use_32bit_io	= true,

	.quirks		= S3C64XX_SPI_QUIRK_CS_AUTO,

};



static const struct platform_device_id s3c64xx_spi_driver_ids[] = {

	{

		.name		= "s3c2443-spi",
@@ -1546,6 +1559,9 @@ static const struct platform_device_id s3c64xx_spi_driver_ids[] = { 
};



static const struct of_device_id s3c64xx_spi_dt_match[] = {

	{ .compatible = "google,gs101-spi",

			.data = &gs101_spi_port_config,

	},

	{ .compatible = "samsung,s3c2443-spi",

			.data = (void *)&s3c2443_spi_port_config,

	},