Commit e02bfea4 authored by Barnabás Czémán's avatar Barnabás Czémán Committed by Bjorn Andersson
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clk: qcom: clk-alpha-pll: Fix pll post div mask when width is not set 



Many qcom clock drivers do not have .width set. In that case value of
(p)->width - 1 will be negative which breaks clock tree. Fix this
by checking if width is zero, and pass 3 to GENMASK if that's the case.

Fixes: 1c354114 ("clk: qcom: support for 2 bit PLL post divider")
Signed-off-by: default avatarBarnabás Czémán <barnabas.czeman@mainlining.org>
Reviewed-by: default avatarDmitry Baryshkov <dmitry.baryshkov@linaro.org>
Reviewed-by: default avatarChristopher Obbard <christopher.obbard@linaro.org>
Tested-by: default avatarChristopher Obbard <christopher.obbard@linaro.org>
Link: https://lore.kernel.org/r/20241006-fix-postdiv-mask-v3-1-160354980433@mainlining.org


Signed-off-by: default avatarBjorn Andersson <andersson@kernel.org>
parent f903663a

drivers/clk/qcom/clk-alpha-pll.c

+1 −1
Original line number Diff line number Diff line
@@ -40,7 +40,7 @@ 


#define PLL_USER_CTL(p)		((p)->offset + (p)->regs[PLL_OFF_USER_CTL])

# define PLL_POST_DIV_SHIFT	8

# define PLL_POST_DIV_MASK(p)	GENMASK((p)->width - 1, 0)

# define PLL_POST_DIV_MASK(p)	GENMASK((p)->width ? (p)->width - 1 : 3, 0)

# define PLL_ALPHA_MSB		BIT(15)

# define PLL_ALPHA_EN		BIT(24)

# define PLL_ALPHA_MODE		BIT(25)