Commit e05021a8 authored by Jakub Kicinski's avatar Jakub Kicinski
Browse files

Merge branch 'net-stmmac-qcon-ethqos-rgmii-accessor-cleanups' 

Russell King says:

====================
net: stmmac: qcon-ethqos: "rgmii" accessor cleanups

This series cleans up the "rgmii" accessors in qcom-ethqos.

readl() and writel() return and take a u32 for the value. Rather than
implicitly casting this to an int, keep it as a u32.

Add set/clear functions to reduce the code and make it easier to read.

Finally, convert the open-coded poll loops to use the iopoll helpers.

Note that patch 1 has a checkpatch warning concerning "volatile" -
I'm changing the type here, and the "volatile" is removed in patch 3.
I do not feel it is appropriate to remove it in patch 1.
====================

Link: https://patch.msgid.link/aR76i0HjXitfl7xk@shell.armlinux.org.uk


Signed-off-by: default avatarJakub Kicinski <kuba@kernel.org>
parents 501253b6 9b60ba51

drivers/net/ethernet/stmicro/stmmac/dwmac-qcom-ethqos.c

+110 −135
Original line number Diff line number Diff line
@@ -116,27 +116,39 @@ struct qcom_ethqos { 
	bool needs_sgmii_loopback;

};



static int rgmii_readl(struct qcom_ethqos *ethqos, unsigned int offset)

static u32 rgmii_readl(struct qcom_ethqos *ethqos, unsigned int offset)

{

	return readl(ethqos->rgmii_base + offset);

}



static void rgmii_writel(struct qcom_ethqos *ethqos,

			 int value, unsigned int offset)

static void rgmii_writel(struct qcom_ethqos *ethqos, u32 value,

			 unsigned int offset)

{

	writel(value, ethqos->rgmii_base + offset);

}



static void rgmii_updatel(struct qcom_ethqos *ethqos,

			  int mask, int val, unsigned int offset)

static void rgmii_updatel(struct qcom_ethqos *ethqos, u32 mask, u32 val,

			  unsigned int offset)

{

	unsigned int temp;

	u32 temp;



	temp = rgmii_readl(ethqos, offset);

	temp = (temp & ~(mask)) | val;

	rgmii_writel(ethqos, temp, offset);

}



static void rgmii_setmask(struct qcom_ethqos *ethqos, u32 mask,

			  unsigned int offset)

{

	rgmii_updatel(ethqos, mask, mask, offset);

}



static void rgmii_clrmask(struct qcom_ethqos *ethqos, u32 mask,

			  unsigned int offset)

{

	rgmii_updatel(ethqos, mask, 0, offset);

}



static void rgmii_dump(void *priv)

{

	struct qcom_ethqos *ethqos = priv;
@@ -194,8 +206,7 @@ qcom_ethqos_set_sgmii_loopback(struct qcom_ethqos *ethqos, bool enable) 
static void ethqos_set_func_clk_en(struct qcom_ethqos *ethqos)

{

	qcom_ethqos_set_sgmii_loopback(ethqos, true);

	rgmii_updatel(ethqos, RGMII_CONFIG_FUNC_CLK_EN,

		      RGMII_CONFIG_FUNC_CLK_EN, RGMII_IO_MACRO_CONFIG);

	rgmii_setmask(ethqos, RGMII_CONFIG_FUNC_CLK_EN, RGMII_IO_MACRO_CONFIG);

}



static const struct ethqos_emac_por emac_v2_3_0_por[] = {
@@ -300,69 +311,55 @@ static const struct ethqos_emac_driver_data emac_v4_0_0_data = { 
static int ethqos_dll_configure(struct qcom_ethqos *ethqos)

{

	struct device *dev = &ethqos->pdev->dev;

	unsigned int val;

	int retry = 1000;

	u32 val;



	/* Set CDR_EN */

	rgmii_updatel(ethqos, SDCC_DLL_CONFIG_CDR_EN,

		      SDCC_DLL_CONFIG_CDR_EN, SDCC_HC_REG_DLL_CONFIG);

	rgmii_setmask(ethqos, SDCC_DLL_CONFIG_CDR_EN, SDCC_HC_REG_DLL_CONFIG);



	/* Set CDR_EXT_EN */

	rgmii_updatel(ethqos, SDCC_DLL_CONFIG_CDR_EXT_EN,

		      SDCC_DLL_CONFIG_CDR_EXT_EN, SDCC_HC_REG_DLL_CONFIG);

	rgmii_setmask(ethqos, SDCC_DLL_CONFIG_CDR_EXT_EN,

		      SDCC_HC_REG_DLL_CONFIG);



	/* Clear CK_OUT_EN */

	rgmii_updatel(ethqos, SDCC_DLL_CONFIG_CK_OUT_EN,

		      0, SDCC_HC_REG_DLL_CONFIG);

	rgmii_clrmask(ethqos, SDCC_DLL_CONFIG_CK_OUT_EN,

		      SDCC_HC_REG_DLL_CONFIG);



	/* Set DLL_EN */

	rgmii_updatel(ethqos, SDCC_DLL_CONFIG_DLL_EN,

		      SDCC_DLL_CONFIG_DLL_EN, SDCC_HC_REG_DLL_CONFIG);

	rgmii_setmask(ethqos, SDCC_DLL_CONFIG_DLL_EN, SDCC_HC_REG_DLL_CONFIG);



	if (!ethqos->has_emac_ge_3) {

		rgmii_updatel(ethqos, SDCC_DLL_MCLK_GATING_EN,

			      0, SDCC_HC_REG_DLL_CONFIG);

		rgmii_clrmask(ethqos, SDCC_DLL_MCLK_GATING_EN,

			      SDCC_HC_REG_DLL_CONFIG);



		rgmii_updatel(ethqos, SDCC_DLL_CDR_FINE_PHASE,

			      0, SDCC_HC_REG_DLL_CONFIG);

		rgmii_clrmask(ethqos, SDCC_DLL_CDR_FINE_PHASE,

			      SDCC_HC_REG_DLL_CONFIG);

	}



	/* Wait for CK_OUT_EN clear */

	do {

		val = rgmii_readl(ethqos, SDCC_HC_REG_DLL_CONFIG);

		val &= SDCC_DLL_CONFIG_CK_OUT_EN;

		if (!val)

			break;

		mdelay(1);

		retry--;

	} while (retry > 0);

	if (!retry)

	if (read_poll_timeout_atomic(rgmii_readl, val,

				     !(val & SDCC_DLL_CONFIG_CK_OUT_EN),

				     1000, 1000000, false,

				     ethqos, SDCC_HC_REG_DLL_CONFIG))

		dev_err(dev, "Clear CK_OUT_EN timedout\n");



	/* Set CK_OUT_EN */

	rgmii_updatel(ethqos, SDCC_DLL_CONFIG_CK_OUT_EN,

		      SDCC_DLL_CONFIG_CK_OUT_EN, SDCC_HC_REG_DLL_CONFIG);

	rgmii_setmask(ethqos, SDCC_DLL_CONFIG_CK_OUT_EN,

		      SDCC_HC_REG_DLL_CONFIG);



	/* Wait for CK_OUT_EN set */

	retry = 1000;

	do {

		val = rgmii_readl(ethqos, SDCC_HC_REG_DLL_CONFIG);

		val &= SDCC_DLL_CONFIG_CK_OUT_EN;

		if (val)

			break;

		mdelay(1);

		retry--;

	} while (retry > 0);

	if (!retry)

	if (read_poll_timeout_atomic(rgmii_readl, val,

				     val & SDCC_DLL_CONFIG_CK_OUT_EN,

				     1000, 1000000, false,

				     ethqos, SDCC_HC_REG_DLL_CONFIG))

		dev_err(dev, "Set CK_OUT_EN timedout\n");



	/* Set DDR_CAL_EN */

	rgmii_updatel(ethqos, SDCC_DLL_CONFIG2_DDR_CAL_EN,

		      SDCC_DLL_CONFIG2_DDR_CAL_EN, SDCC_HC_REG_DLL_CONFIG2);

	rgmii_setmask(ethqos, SDCC_DLL_CONFIG2_DDR_CAL_EN,

		      SDCC_HC_REG_DLL_CONFIG2);



	if (!ethqos->has_emac_ge_3) {

		rgmii_updatel(ethqos, SDCC_DLL_CONFIG2_DLL_CLOCK_DIS,

			      0, SDCC_HC_REG_DLL_CONFIG2);

		rgmii_clrmask(ethqos, SDCC_DLL_CONFIG2_DLL_CLOCK_DIS,

			      SDCC_HC_REG_DLL_CONFIG2);



		rgmii_updatel(ethqos, SDCC_DLL_CONFIG2_MCLK_FREQ_CALC,

			      0x1A << 10, SDCC_HC_REG_DLL_CONFIG2);
@@ -370,8 +367,7 @@ static int ethqos_dll_configure(struct qcom_ethqos *ethqos) 
		rgmii_updatel(ethqos, SDCC_DLL_CONFIG2_DDR_TRAFFIC_INIT_SEL,

			      BIT(2), SDCC_HC_REG_DLL_CONFIG2);



		rgmii_updatel(ethqos, SDCC_DLL_CONFIG2_DDR_TRAFFIC_INIT_SW,

			      SDCC_DLL_CONFIG2_DDR_TRAFFIC_INIT_SW,

		rgmii_setmask(ethqos, SDCC_DLL_CONFIG2_DDR_TRAFFIC_INIT_SW,

			      SDCC_HC_REG_DLL_CONFIG2);

	}
@@ -392,8 +388,8 @@ static int ethqos_rgmii_macro_init(struct qcom_ethqos *ethqos, int speed) 
		phase_shift = RGMII_CONFIG2_TX_CLK_PHASE_SHIFT_EN;



	/* Disable loopback mode */

	rgmii_updatel(ethqos, RGMII_CONFIG2_TX_TO_RX_LOOPBACK_EN,

		      0, RGMII_IO_MACRO_CONFIG2);

	rgmii_clrmask(ethqos, RGMII_CONFIG2_TX_TO_RX_LOOPBACK_EN,

		      RGMII_IO_MACRO_CONFIG2);



	/* Determine if this platform wants loopback enabled after programming */

	if (ethqos->rgmii_config_loopback_en)
@@ -402,29 +398,26 @@ static int ethqos_rgmii_macro_init(struct qcom_ethqos *ethqos, int speed) 
		loopback = 0;



	/* Select RGMII, write 0 to interface select */

	rgmii_updatel(ethqos, RGMII_CONFIG_INTF_SEL,

		      0, RGMII_IO_MACRO_CONFIG);

	rgmii_clrmask(ethqos, RGMII_CONFIG_INTF_SEL, RGMII_IO_MACRO_CONFIG);



	switch (speed) {

	case SPEED_1000:

		rgmii_updatel(ethqos, RGMII_CONFIG_DDR_MODE,

			      RGMII_CONFIG_DDR_MODE, RGMII_IO_MACRO_CONFIG);

		rgmii_updatel(ethqos, RGMII_CONFIG_BYPASS_TX_ID_EN,

			      0, RGMII_IO_MACRO_CONFIG);

		rgmii_updatel(ethqos, RGMII_CONFIG_POS_NEG_DATA_SEL,

			      RGMII_CONFIG_POS_NEG_DATA_SEL,

		rgmii_setmask(ethqos, RGMII_CONFIG_DDR_MODE,

			      RGMII_IO_MACRO_CONFIG);

		rgmii_clrmask(ethqos, RGMII_CONFIG_BYPASS_TX_ID_EN,

			      RGMII_IO_MACRO_CONFIG);

		rgmii_setmask(ethqos, RGMII_CONFIG_POS_NEG_DATA_SEL,

			      RGMII_IO_MACRO_CONFIG);

		rgmii_updatel(ethqos, RGMII_CONFIG_PROG_SWAP,

			      RGMII_CONFIG_PROG_SWAP, RGMII_IO_MACRO_CONFIG);

		rgmii_updatel(ethqos, RGMII_CONFIG2_DATA_DIVIDE_CLK_SEL,

			      0, RGMII_IO_MACRO_CONFIG2);

		rgmii_setmask(ethqos, RGMII_CONFIG_PROG_SWAP,

			      RGMII_IO_MACRO_CONFIG);

		rgmii_clrmask(ethqos, RGMII_CONFIG2_DATA_DIVIDE_CLK_SEL,

			      RGMII_IO_MACRO_CONFIG2);



		rgmii_updatel(ethqos, RGMII_CONFIG2_TX_CLK_PHASE_SHIFT_EN,

			      phase_shift, RGMII_IO_MACRO_CONFIG2);

		rgmii_updatel(ethqos, RGMII_CONFIG2_RSVD_CONFIG15,

			      0, RGMII_IO_MACRO_CONFIG2);

		rgmii_updatel(ethqos, RGMII_CONFIG2_RX_PROG_SWAP,

			      RGMII_CONFIG2_RX_PROG_SWAP,

		rgmii_clrmask(ethqos, RGMII_CONFIG2_RSVD_CONFIG15,

			      RGMII_IO_MACRO_CONFIG2);

		rgmii_setmask(ethqos, RGMII_CONFIG2_RX_PROG_SWAP,

			      RGMII_IO_MACRO_CONFIG2);



		/* PRG_RCLK_DLY = TCXO period * TCXO_CYCLES_CNT / 2 * RX delay ns,
@@ -439,87 +432,78 @@ static int ethqos_rgmii_macro_init(struct qcom_ethqos *ethqos, int speed) 
			rgmii_updatel(ethqos, SDCC_DDR_CONFIG_PRG_RCLK_DLY,

				      57, SDCC_HC_REG_DDR_CONFIG);

		}

		rgmii_updatel(ethqos, SDCC_DDR_CONFIG_PRG_DLY_EN,

			      SDCC_DDR_CONFIG_PRG_DLY_EN,

		rgmii_setmask(ethqos, SDCC_DDR_CONFIG_PRG_DLY_EN,

			      SDCC_HC_REG_DDR_CONFIG);

		rgmii_updatel(ethqos, RGMII_CONFIG_LOOPBACK_EN,

			      loopback, RGMII_IO_MACRO_CONFIG);

		break;



	case SPEED_100:

		rgmii_updatel(ethqos, RGMII_CONFIG_DDR_MODE,

			      RGMII_CONFIG_DDR_MODE, RGMII_IO_MACRO_CONFIG);

		rgmii_updatel(ethqos, RGMII_CONFIG_BYPASS_TX_ID_EN,

			      RGMII_CONFIG_BYPASS_TX_ID_EN,

		rgmii_setmask(ethqos, RGMII_CONFIG_DDR_MODE,

			      RGMII_IO_MACRO_CONFIG);

		rgmii_setmask(ethqos, RGMII_CONFIG_BYPASS_TX_ID_EN,

			      RGMII_IO_MACRO_CONFIG);

		rgmii_clrmask(ethqos, RGMII_CONFIG_POS_NEG_DATA_SEL,

			      RGMII_IO_MACRO_CONFIG);

		rgmii_updatel(ethqos, RGMII_CONFIG_POS_NEG_DATA_SEL,

			      0, RGMII_IO_MACRO_CONFIG);

		rgmii_updatel(ethqos, RGMII_CONFIG_PROG_SWAP,

			      0, RGMII_IO_MACRO_CONFIG);

		rgmii_updatel(ethqos, RGMII_CONFIG2_DATA_DIVIDE_CLK_SEL,

			      0, RGMII_IO_MACRO_CONFIG2);

		rgmii_clrmask(ethqos, RGMII_CONFIG_PROG_SWAP,

			      RGMII_IO_MACRO_CONFIG);

		rgmii_clrmask(ethqos, RGMII_CONFIG2_DATA_DIVIDE_CLK_SEL,

			      RGMII_IO_MACRO_CONFIG2);

		rgmii_updatel(ethqos, RGMII_CONFIG2_TX_CLK_PHASE_SHIFT_EN,

			      phase_shift, RGMII_IO_MACRO_CONFIG2);

		rgmii_updatel(ethqos, RGMII_CONFIG_MAX_SPD_PRG_2,

			      BIT(6), RGMII_IO_MACRO_CONFIG);

		rgmii_updatel(ethqos, RGMII_CONFIG2_RSVD_CONFIG15,

			      0, RGMII_IO_MACRO_CONFIG2);

		rgmii_clrmask(ethqos, RGMII_CONFIG2_RSVD_CONFIG15,

			      RGMII_IO_MACRO_CONFIG2);



		if (ethqos->has_emac_ge_3)

			rgmii_updatel(ethqos, RGMII_CONFIG2_RX_PROG_SWAP,

				      RGMII_CONFIG2_RX_PROG_SWAP,

			rgmii_setmask(ethqos, RGMII_CONFIG2_RX_PROG_SWAP,

				      RGMII_IO_MACRO_CONFIG2);

		else

			rgmii_updatel(ethqos, RGMII_CONFIG2_RX_PROG_SWAP,

				      0, RGMII_IO_MACRO_CONFIG2);

			rgmii_clrmask(ethqos, RGMII_CONFIG2_RX_PROG_SWAP,

				      RGMII_IO_MACRO_CONFIG2);



		/* Write 0x5 to PRG_RCLK_DLY_CODE */

		rgmii_updatel(ethqos, SDCC_DDR_CONFIG_EXT_PRG_RCLK_DLY_CODE,

			      (BIT(29) | BIT(27)), SDCC_HC_REG_DDR_CONFIG);

		rgmii_updatel(ethqos, SDCC_DDR_CONFIG_EXT_PRG_RCLK_DLY,

			      SDCC_DDR_CONFIG_EXT_PRG_RCLK_DLY,

		rgmii_setmask(ethqos, SDCC_DDR_CONFIG_EXT_PRG_RCLK_DLY,

			      SDCC_HC_REG_DDR_CONFIG);

		rgmii_updatel(ethqos, SDCC_DDR_CONFIG_EXT_PRG_RCLK_DLY_EN,

			      SDCC_DDR_CONFIG_EXT_PRG_RCLK_DLY_EN,

		rgmii_setmask(ethqos, SDCC_DDR_CONFIG_EXT_PRG_RCLK_DLY_EN,

			      SDCC_HC_REG_DDR_CONFIG);

		rgmii_updatel(ethqos, RGMII_CONFIG_LOOPBACK_EN,

			      loopback, RGMII_IO_MACRO_CONFIG);

		break;



	case SPEED_10:

		rgmii_updatel(ethqos, RGMII_CONFIG_DDR_MODE,

			      RGMII_CONFIG_DDR_MODE, RGMII_IO_MACRO_CONFIG);

		rgmii_updatel(ethqos, RGMII_CONFIG_BYPASS_TX_ID_EN,

			      RGMII_CONFIG_BYPASS_TX_ID_EN,

		rgmii_setmask(ethqos, RGMII_CONFIG_DDR_MODE,

			      RGMII_IO_MACRO_CONFIG);

		rgmii_setmask(ethqos, RGMII_CONFIG_BYPASS_TX_ID_EN,

			      RGMII_IO_MACRO_CONFIG);

		rgmii_clrmask(ethqos, RGMII_CONFIG_POS_NEG_DATA_SEL,

			      RGMII_IO_MACRO_CONFIG);

		rgmii_clrmask(ethqos, RGMII_CONFIG_PROG_SWAP,

			      RGMII_IO_MACRO_CONFIG);

		rgmii_updatel(ethqos, RGMII_CONFIG_POS_NEG_DATA_SEL,

			      0, RGMII_IO_MACRO_CONFIG);

		rgmii_updatel(ethqos, RGMII_CONFIG_PROG_SWAP,

			      0, RGMII_IO_MACRO_CONFIG);

		rgmii_updatel(ethqos, RGMII_CONFIG2_DATA_DIVIDE_CLK_SEL,

			      0, RGMII_IO_MACRO_CONFIG2);

		rgmii_clrmask(ethqos, RGMII_CONFIG2_DATA_DIVIDE_CLK_SEL,

			      RGMII_IO_MACRO_CONFIG2);

		rgmii_updatel(ethqos, RGMII_CONFIG2_TX_CLK_PHASE_SHIFT_EN,

			      phase_shift, RGMII_IO_MACRO_CONFIG2);

		rgmii_updatel(ethqos, RGMII_CONFIG_MAX_SPD_PRG_9,

			      BIT(12) | GENMASK(9, 8),

			      RGMII_IO_MACRO_CONFIG);

		rgmii_updatel(ethqos, RGMII_CONFIG2_RSVD_CONFIG15,

			      0, RGMII_IO_MACRO_CONFIG2);

		rgmii_clrmask(ethqos, RGMII_CONFIG2_RSVD_CONFIG15,

			      RGMII_IO_MACRO_CONFIG2);

		if (ethqos->has_emac_ge_3)

			rgmii_updatel(ethqos, RGMII_CONFIG2_RX_PROG_SWAP,

				      RGMII_CONFIG2_RX_PROG_SWAP,

			rgmii_setmask(ethqos, RGMII_CONFIG2_RX_PROG_SWAP,

				      RGMII_IO_MACRO_CONFIG2);

		else

			rgmii_updatel(ethqos, RGMII_CONFIG2_RX_PROG_SWAP,

				      0, RGMII_IO_MACRO_CONFIG2);

			rgmii_clrmask(ethqos, RGMII_CONFIG2_RX_PROG_SWAP,

				      RGMII_IO_MACRO_CONFIG2);

		/* Write 0x5 to PRG_RCLK_DLY_CODE */

		rgmii_updatel(ethqos, SDCC_DDR_CONFIG_EXT_PRG_RCLK_DLY_CODE,

			      (BIT(29) | BIT(27)), SDCC_HC_REG_DDR_CONFIG);

		rgmii_updatel(ethqos, SDCC_DDR_CONFIG_EXT_PRG_RCLK_DLY,

			      SDCC_DDR_CONFIG_EXT_PRG_RCLK_DLY,

		rgmii_setmask(ethqos, SDCC_DDR_CONFIG_EXT_PRG_RCLK_DLY,

			      SDCC_HC_REG_DDR_CONFIG);

		rgmii_updatel(ethqos, SDCC_DDR_CONFIG_EXT_PRG_RCLK_DLY_EN,

			      SDCC_DDR_CONFIG_EXT_PRG_RCLK_DLY_EN,

		rgmii_setmask(ethqos, SDCC_DDR_CONFIG_EXT_PRG_RCLK_DLY_EN,

			      SDCC_HC_REG_DDR_CONFIG);

		rgmii_updatel(ethqos, RGMII_CONFIG_LOOPBACK_EN,

			      loopback, RGMII_IO_MACRO_CONFIG);
@@ -535,8 +519,8 @@ static int ethqos_rgmii_macro_init(struct qcom_ethqos *ethqos, int speed) 
static int ethqos_configure_rgmii(struct qcom_ethqos *ethqos, int speed)

{

	struct device *dev = &ethqos->pdev->dev;

	volatile unsigned int dll_lock;

	unsigned int i, retry = 1000;

	unsigned int i;

	u32 val;



	/* Reset to POR values and enable clk */

	for (i = 0; i < ethqos->num_por; i++)
@@ -547,12 +531,12 @@ static int ethqos_configure_rgmii(struct qcom_ethqos *ethqos, int speed) 
	/* Initialize the DLL first */



	/* Set DLL_RST */

	rgmii_updatel(ethqos, SDCC_DLL_CONFIG_DLL_RST,

		      SDCC_DLL_CONFIG_DLL_RST, SDCC_HC_REG_DLL_CONFIG);

	rgmii_setmask(ethqos, SDCC_DLL_CONFIG_DLL_RST,

		      SDCC_HC_REG_DLL_CONFIG);



	/* Set PDN */

	rgmii_updatel(ethqos, SDCC_DLL_CONFIG_PDN,

		      SDCC_DLL_CONFIG_PDN, SDCC_HC_REG_DLL_CONFIG);

	rgmii_setmask(ethqos, SDCC_DLL_CONFIG_PDN,

		      SDCC_HC_REG_DLL_CONFIG);



	if (ethqos->has_emac_ge_3) {

		if (speed == SPEED_1000) {
@@ -566,21 +550,18 @@ static int ethqos_configure_rgmii(struct qcom_ethqos *ethqos, int speed) 
	}



	/* Clear DLL_RST */

	rgmii_updatel(ethqos, SDCC_DLL_CONFIG_DLL_RST, 0,

		      SDCC_HC_REG_DLL_CONFIG);

	rgmii_clrmask(ethqos, SDCC_DLL_CONFIG_DLL_RST, SDCC_HC_REG_DLL_CONFIG);



	/* Clear PDN */

	rgmii_updatel(ethqos, SDCC_DLL_CONFIG_PDN, 0,

		      SDCC_HC_REG_DLL_CONFIG);

	rgmii_clrmask(ethqos, SDCC_DLL_CONFIG_PDN, SDCC_HC_REG_DLL_CONFIG);



	if (speed != SPEED_100 && speed != SPEED_10) {

		/* Set DLL_EN */

		rgmii_updatel(ethqos, SDCC_DLL_CONFIG_DLL_EN,

			      SDCC_DLL_CONFIG_DLL_EN, SDCC_HC_REG_DLL_CONFIG);

		rgmii_setmask(ethqos, SDCC_DLL_CONFIG_DLL_EN,

			      SDCC_HC_REG_DLL_CONFIG);



		/* Set CK_OUT_EN */

		rgmii_updatel(ethqos, SDCC_DLL_CONFIG_CK_OUT_EN,

			      SDCC_DLL_CONFIG_CK_OUT_EN,

		rgmii_setmask(ethqos, SDCC_DLL_CONFIG_CK_OUT_EN,

			      SDCC_HC_REG_DLL_CONFIG);



		/* Set USR_CTL bit 26 with mask of 3 bits */
@@ -589,14 +570,10 @@ static int ethqos_configure_rgmii(struct qcom_ethqos *ethqos, int speed) 
				      SDCC_USR_CTL);



		/* wait for DLL LOCK */

		do {

			mdelay(1);

			dll_lock = rgmii_readl(ethqos, SDC4_STATUS);

			if (dll_lock & SDC4_STATUS_DLL_LOCK)

				break;

			retry--;

		} while (retry > 0);

		if (!retry)

		if (read_poll_timeout_atomic(rgmii_readl, val,

					     val & SDC4_STATUS_DLL_LOCK,

					     1000, 1000000, true,

					     ethqos, SDC4_STATUS))

			dev_err(dev, "Timeout while waiting for DLL lock\n");

	}
@@ -631,15 +608,13 @@ static int ethqos_configure_sgmii(struct qcom_ethqos *ethqos, int speed) 


	switch (speed) {

	case SPEED_2500:

		rgmii_updatel(ethqos, RGMII_CONFIG2_RGMII_CLK_SEL_CFG,

			      RGMII_CONFIG2_RGMII_CLK_SEL_CFG,

		rgmii_setmask(ethqos, RGMII_CONFIG2_RGMII_CLK_SEL_CFG,

			      RGMII_IO_MACRO_CONFIG2);

		ethqos_set_serdes_speed(ethqos, SPEED_2500);

		ethqos_pcs_set_inband(priv, false);

		break;

	case SPEED_1000:

		rgmii_updatel(ethqos, RGMII_CONFIG2_RGMII_CLK_SEL_CFG,

			      RGMII_CONFIG2_RGMII_CLK_SEL_CFG,

		rgmii_setmask(ethqos, RGMII_CONFIG2_RGMII_CLK_SEL_CFG,

			      RGMII_IO_MACRO_CONFIG2);

		ethqos_set_serdes_speed(ethqos, SPEED_1000);

		ethqos_pcs_set_inband(priv, true);