Commit e0a50498 authored by Yao Zihong's avatar Yao Zihong Committed by Paul Walmsley
Browse files

riscv: hwprobe: Expose Zicbop extension and its block size 



- Add `RISCV_HWPROBE_EXT_ZICBOP` to report the presence of the
  Zicbop extension.
- Add `RISCV_HWPROBE_KEY_ZICBOP_BLOCK_SIZE` to expose the block
  size (in bytes) when Zicbop is supported.
- Update hwprobe.rst to document the new extension bit and block
  size key, following the existing Zicbom/Zicboz style.

Reviewed-by: default avatarAndrew Jones <ajones@ventanamicro.com>
Signed-off-by: default avatarYao Zihong <zihong.plct@isrc.iscas.ac.cn>
Link: https://patch.msgid.link/20251118162436.15485-2-zihong.plct@isrc.iscas.ac.cn


[pjw@kernel.org: updated to apply]
Signed-off-by: default avatarPaul Walmsley <pjw@kernel.org>
parent ad1bb4b8

Documentation/arch/riscv/hwprobe.rst

+6 −0
Original line number Diff line number Diff line
@@ -278,6 +278,9 @@ The following keys are defined: 
       ratified in commit 49f49c842ff9 ("Update to Rafified state") of

       riscv-zabha.



  * :c:macro:`RISCV_HWPROBE_EXT_ZICBOP`: The Zicbop extension is supported, as

       ratified in commit 3dd606f ("Create cmobase-v1.0.pdf") of riscv-CMOs.



* :c:macro:`RISCV_HWPROBE_KEY_CPUPERF_0`: Deprecated.  Returns similar values to

     :c:macro:`RISCV_HWPROBE_KEY_MISALIGNED_SCALAR_PERF`, but the key was

     mistakenly classified as a bitmask rather than a value.
@@ -373,3 +376,6 @@ The following keys are defined: 
    * :c:macro:`RISCV_HWPROBE_VENDOR_EXT_XSFVFWMACCQQQ`: The Xsfvfwmaccqqq

        vendor extension is supported in version 1.0 of Matrix Multiply Accumulate

	Instruction Extensions Specification.



* :c:macro:`RISCV_HWPROBE_KEY_ZICBOP_BLOCK_SIZE`: An unsigned int which

  represents the size of the Zicbop block in bytes.

arch/riscv/include/asm/hwprobe.h

+1 −1
Original line number Diff line number Diff line
@@ -8,7 +8,7 @@ 


#include <uapi/asm/hwprobe.h>



#define RISCV_HWPROBE_MAX_KEY 14

#define RISCV_HWPROBE_MAX_KEY 15



static inline bool riscv_hwprobe_key_is_valid(__s64 key)

{

arch/riscv/include/uapi/asm/hwprobe.h

+2 −0
Original line number Diff line number Diff line
@@ -83,6 +83,7 @@ struct riscv_hwprobe { 
#define		RISCV_HWPROBE_EXT_ZALRSC	(1ULL << 57)

#define		RISCV_HWPROBE_EXT_ZABHA		(1ULL << 58)

#define		RISCV_HWPROBE_EXT_ZALASR	(1ULL << 59)

#define		RISCV_HWPROBE_EXT_ZICBOP	(1ULL << 60)

#define RISCV_HWPROBE_KEY_CPUPERF_0	5

#define		RISCV_HWPROBE_MISALIGNED_UNKNOWN	(0 << 0)

#define		RISCV_HWPROBE_MISALIGNED_EMULATED	(1 << 0)
@@ -108,6 +109,7 @@ struct riscv_hwprobe { 
#define RISCV_HWPROBE_KEY_ZICBOM_BLOCK_SIZE	12

#define RISCV_HWPROBE_KEY_VENDOR_EXT_SIFIVE_0	13

#define RISCV_HWPROBE_KEY_VENDOR_EXT_MIPS_0	14

#define RISCV_HWPROBE_KEY_ZICBOP_BLOCK_SIZE	15

/* Increase RISCV_HWPROBE_MAX_KEY when adding items. */



/* Flags */

arch/riscv/kernel/sys_hwprobe.c

+6 −0
Original line number Diff line number Diff line
@@ -123,6 +123,7 @@ static void hwprobe_isa_ext0(struct riscv_hwprobe *pair, 
		EXT_KEY(ZCB);

		EXT_KEY(ZCMOP);

		EXT_KEY(ZICBOM);

		EXT_KEY(ZICBOP);

		EXT_KEY(ZICBOZ);

		EXT_KEY(ZICNTR);

		EXT_KEY(ZICOND);
@@ -303,6 +304,11 @@ static void hwprobe_one_pair(struct riscv_hwprobe *pair, 
		if (hwprobe_ext0_has(cpus, RISCV_HWPROBE_EXT_ZICBOM))

			pair->value = riscv_cbom_block_size;

		break;

	case RISCV_HWPROBE_KEY_ZICBOP_BLOCK_SIZE:

		pair->value = 0;

		if (hwprobe_ext0_has(cpus, RISCV_HWPROBE_EXT_ZICBOP))

			pair->value = riscv_cbop_block_size;

		break;

	case RISCV_HWPROBE_KEY_HIGHEST_VIRT_ADDRESS:

		pair->value = user_max_virt_addr();

		break;