Commit e0bb80c6 authored by Kristina Martsenko's avatar Kristina Martsenko Committed by Oliver Upton
Browse files

KVM: arm64: Expose MOPS instructions to guests 



Expose the Armv8.8 FEAT_MOPS feature to guests in the ID register and
allow the MOPS instructions to be run in a guest. Only expose MOPS if
the whole system supports it.

Note, it is expected that guests do not use these instructions on MMIO,
similarly to other instructions where ESR_EL2.ISV==0 such as LDP/STP.

Signed-off-by: default avatarKristina Martsenko <kristina.martsenko@arm.com>
Reviewed-by: default avatarMarc Zyngier <maz@kernel.org>
Link: https://lore.kernel.org/r/20230922112508.1774352-3-kristina.martsenko@arm.com


Signed-off-by: default avatarOliver Upton <oliver.upton@linux.dev>
parent 2de451a3

arch/arm64/include/asm/kvm_arm.h

+3 −1
Original line number Diff line number Diff line
@@ -102,7 +102,9 @@ 
#define HCR_HOST_NVHE_PROTECTED_FLAGS (HCR_HOST_NVHE_FLAGS | HCR_TSC)

#define HCR_HOST_VHE_FLAGS (HCR_RW | HCR_TGE | HCR_E2H)



#define HCRX_GUEST_FLAGS (HCRX_EL2_SMPME | HCRX_EL2_TCR2En)

#define HCRX_GUEST_FLAGS \

	(HCRX_EL2_SMPME | HCRX_EL2_TCR2En | \

	 (cpus_have_final_cap(ARM64_HAS_MOPS) ? (HCRX_EL2_MSCEn | HCRX_EL2_MCE2) : 0))

#define HCRX_HOST_FLAGS (HCRX_EL2_MSCEn | HCRX_EL2_TCR2En)



/* TCR_EL2 Registers bits */

arch/arm64/kvm/hyp/include/nvhe/fixed_config.h

+2 −1
Original line number Diff line number Diff line
@@ -197,7 +197,8 @@ 


#define PVM_ID_AA64ISAR2_ALLOW (\

	ARM64_FEATURE_MASK(ID_AA64ISAR2_EL1_GPA3) | \

	ARM64_FEATURE_MASK(ID_AA64ISAR2_EL1_APA3) \

	ARM64_FEATURE_MASK(ID_AA64ISAR2_EL1_APA3) | \

	ARM64_FEATURE_MASK(ID_AA64ISAR2_EL1_MOPS) \

	)



u64 pvm_read_id_reg(const struct kvm_vcpu *vcpu, u32 id);

arch/arm64/kvm/sys_regs.c

+0 −2
Original line number Diff line number Diff line
@@ -1344,7 +1344,6 @@ static u64 __kvm_read_sanitised_id_reg(const struct kvm_vcpu *vcpu, 
				 ARM64_FEATURE_MASK(ID_AA64ISAR2_EL1_GPA3));

		if (!cpus_have_final_cap(ARM64_HAS_WFXT))

			val &= ~ARM64_FEATURE_MASK(ID_AA64ISAR2_EL1_WFxT);

		val &= ~ARM64_FEATURE_MASK(ID_AA64ISAR2_EL1_MOPS);

		break;

	case SYS_ID_AA64MMFR2_EL1:

		val &= ~ID_AA64MMFR2_EL1_CCIDX_MASK;
@@ -2095,7 +2094,6 @@ static const struct sys_reg_desc sys_reg_descs[] = { 
					ID_AA64ISAR1_EL1_API |

					ID_AA64ISAR1_EL1_APA)),

	ID_WRITABLE(ID_AA64ISAR2_EL1, ~(ID_AA64ISAR2_EL1_RES0 |

					ID_AA64ISAR2_EL1_MOPS |

					ID_AA64ISAR2_EL1_APA3 |

					ID_AA64ISAR2_EL1_GPA3)),

	ID_UNALLOCATED(6,3),