Commit e15d09f5 authored by Roman Li's avatar Roman Li Committed by Alex Deucher
Browse files

drm/amd/display: enable phy-ssc reduction by default 



[Why]
Reduction of phy-ssc is needed to support DP2 high pixel clock on dcn35x/36.
There's a special flag to enable it in dmub hw params.

[How]
Set hbr3_phy_ssc to true for dcn35, dcn351 and dcn36.

Reviewed-by: default avatarCharlene Liu <charlene.liu@amd.com>
Signed-off-by: default avatarRoman Li <Roman.Li@amd.com>
Signed-off-by: default avatarZaeem Mohamed <zaeem.mohamed@amd.com>
Tested-by: default avatarMark Broadworth <mark.broadworth@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent cd74ce1f

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

+1 −0
Original line number Diff line number Diff line
@@ -1330,6 +1330,7 @@ static int dm_dmub_hw_init(struct amdgpu_device *adev) 
	case IP_VERSION(3, 5, 1):

	case IP_VERSION(3, 6, 0):

		hw_params.ips_sequential_ono = adev->external_rev_id > 0x10;

		hw_params.lower_hbr3_phy_ssc = true;

		break;

	default:

		break;