Commit e15ec812 authored by Sunil Khatri's avatar Sunil Khatri Committed by Alex Deucher
Browse files

drm/amdgpu: update the handle ptr in post_soft_reset 



Update the *handle to amdgpu_ip_block ptr for all
functions pointers of post_soft_reset.

Signed-off-by: default avatarSunil Khatri <sunil.khatri@amd.com>
Reviewed-by: default avatarChristian König <christian.koenig@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 0ef2a1e7

drivers/gpu/drm/amd/amdgpu/amdgpu_device.c

+1 −1
Original line number Diff line number Diff line
@@ -5070,7 +5070,7 @@ static int amdgpu_device_ip_post_soft_reset(struct amdgpu_device *adev) 
			continue;

		if (adev->ip_blocks[i].status.hang &&

		    adev->ip_blocks[i].version->funcs->post_soft_reset)

			r = adev->ip_blocks[i].version->funcs->post_soft_reset(adev);

			r = adev->ip_blocks[i].version->funcs->post_soft_reset(&adev->ip_blocks[i]);

		if (r)

			return r;

	}

drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c

+3 −2
Original line number Diff line number Diff line
@@ -4931,12 +4931,13 @@ static bool gfx_v11_0_check_soft_reset(struct amdgpu_ip_block *ip_block) 
	return false;

}



static int gfx_v11_0_post_soft_reset(void *handle)

static int gfx_v11_0_post_soft_reset(struct amdgpu_ip_block *ip_block)

{

	struct amdgpu_device *adev = ip_block->adev;

	/**

	 * GFX soft reset will impact MES, need resume MES when do GFX soft reset

	 */

	return amdgpu_mes_resume((struct amdgpu_device *)handle);

	return amdgpu_mes_resume(adev);

}



static uint64_t gfx_v11_0_get_gpu_clock_counter(struct amdgpu_device *adev)

drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c

+2 −2
Original line number Diff line number Diff line
@@ -5086,9 +5086,9 @@ static int gfx_v8_0_soft_reset(struct amdgpu_ip_block *ip_block) 
	return 0;

}



static int gfx_v8_0_post_soft_reset(void *handle)

static int gfx_v8_0_post_soft_reset(struct amdgpu_ip_block *ip_block)

{

	struct amdgpu_device *adev = (struct amdgpu_device *)handle;

	struct amdgpu_device *adev = ip_block->adev;

	u32 grbm_soft_reset = 0;



	if ((!adev->gfx.grbm_soft_reset) &&

drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c

+2 −2
Original line number Diff line number Diff line
@@ -1361,9 +1361,9 @@ static int gmc_v8_0_soft_reset(struct amdgpu_ip_block *ip_block) 
	return 0;

}



static int gmc_v8_0_post_soft_reset(void *handle)

static int gmc_v8_0_post_soft_reset(struct amdgpu_ip_block *ip_block)

{

	struct amdgpu_device *adev = (struct amdgpu_device *)handle;

	struct amdgpu_device *adev = ip_block->adev;



	if (!adev->gmc.srbm_soft_reset)

		return 0;

drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c

+2 −2
Original line number Diff line number Diff line
@@ -1271,9 +1271,9 @@ static int sdma_v3_0_pre_soft_reset(struct amdgpu_ip_block *ip_block) 
	return 0;

}



static int sdma_v3_0_post_soft_reset(void *handle)

static int sdma_v3_0_post_soft_reset(struct amdgpu_ip_block *ip_block)

{

	struct amdgpu_device *adev = (struct amdgpu_device *)handle;

	struct amdgpu_device *adev = ip_block->adev;

	u32 srbm_soft_reset = 0;



	if (!adev->sdma.srbm_soft_reset)