Commit e1771825 authored by Ma Jun's avatar Ma Jun Committed by Alex Deucher
Browse files

drm/amdgpu/pm: Check the validity of overdiver power limit 



Check the validity of overdriver power limit before using it.

Fixes: 7968e974 ("drm/amdgpu/pm: Fix the power1_min_cap value")
Signed-off-by: default avatarMa Jun <Jun.Ma2@amd.com>
Suggested-by: default avatarLazar Lijo <lijo.lazar@amd.com>
Suggested-by: default avatarAlex Deucher <Alexander.Deucher@amd.com>
Reviewed-by: default avatarAlex Deucher <alexander.deucher@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
Cc: stable@vger.kernel.org
parent 08ae9ef8

drivers/gpu/drm/amd/pm/swsmu/smu11/arcturus_ppt.c

+7 −4
Original line number Diff line number Diff line
@@ -1285,6 +1285,7 @@ static int arcturus_get_power_limit(struct smu_context *smu, 
{

	struct smu_11_0_powerplay_table *powerplay_table =

		(struct smu_11_0_powerplay_table *)smu->smu_table.power_play_table;

	struct smu_11_0_overdrive_table *od_settings = smu->od_settings;

	PPTable_t *pptable = smu->smu_table.driver_pptable;

	uint32_t power_limit, od_percent_upper = 0, od_percent_lower = 0;
@@ -1304,13 +1305,15 @@ static int arcturus_get_power_limit(struct smu_context *smu, 
		*default_power_limit = power_limit;



	if (powerplay_table) {

		if (smu->od_enabled)

		if (smu->od_enabled &&

				od_settings->cap[SMU_11_0_ODCAP_POWER_LIMIT]) {

			od_percent_upper = le32_to_cpu(powerplay_table->overdrive_table.max[SMU_11_0_ODSETTING_POWERPERCENTAGE]);

		else

			od_percent_lower = le32_to_cpu(powerplay_table->overdrive_table.min[SMU_11_0_ODSETTING_POWERPERCENTAGE]);

		} else if (od_settings->cap[SMU_11_0_ODCAP_POWER_LIMIT]) {

			od_percent_upper = 0;



			od_percent_lower = le32_to_cpu(powerplay_table->overdrive_table.min[SMU_11_0_ODSETTING_POWERPERCENTAGE]);

		}

	}



	dev_dbg(smu->adev->dev, "od percent upper:%d, od percent lower:%d (default power: %d)\n",

							od_percent_upper, od_percent_lower, power_limit);

drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c

+5 −4
Original line number Diff line number Diff line
@@ -2358,13 +2358,14 @@ static int navi10_get_power_limit(struct smu_context *smu, 


	if (powerplay_table) {

		if (smu->od_enabled &&

			    navi10_od_feature_is_supported(od_settings, SMU_11_0_ODCAP_POWER_LIMIT))

			    navi10_od_feature_is_supported(od_settings, SMU_11_0_ODCAP_POWER_LIMIT)) {

			od_percent_upper = le32_to_cpu(powerplay_table->overdrive_table.max[SMU_11_0_ODSETTING_POWERPERCENTAGE]);

		else

			od_percent_lower = le32_to_cpu(powerplay_table->overdrive_table.min[SMU_11_0_ODSETTING_POWERPERCENTAGE]);

		} else if (navi10_od_feature_is_supported(od_settings, SMU_11_0_ODCAP_POWER_LIMIT)) {

			od_percent_upper = 0;



			od_percent_lower = le32_to_cpu(powerplay_table->overdrive_table.min[SMU_11_0_ODSETTING_POWERPERCENTAGE]);

		}

	}



	dev_dbg(smu->adev->dev, "od percent upper:%d, od percent lower:%d (default power: %d)\n",

					od_percent_upper, od_percent_lower, power_limit);

drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c

+13 −10
Original line number Diff line number Diff line
@@ -617,6 +617,12 @@ static uint32_t sienna_cichlid_get_throttler_status_locked(struct smu_context *s 
	return throttler_status;

}



static bool sienna_cichlid_is_od_feature_supported(struct smu_11_0_7_overdrive_table *od_table,

						   enum SMU_11_0_7_ODFEATURE_CAP cap)

{

	return od_table->cap[cap];

}



static int sienna_cichlid_get_power_limit(struct smu_context *smu,

					  uint32_t *current_power_limit,

					  uint32_t *default_power_limit,
@@ -625,6 +631,7 @@ static int sienna_cichlid_get_power_limit(struct smu_context *smu, 
{

	struct smu_11_0_7_powerplay_table *powerplay_table =

		(struct smu_11_0_7_powerplay_table *)smu->smu_table.power_play_table;

	struct smu_11_0_7_overdrive_table *od_settings = smu->od_settings;

	uint32_t power_limit, od_percent_upper = 0, od_percent_lower = 0;

	uint16_t *table_member;
@@ -641,13 +648,15 @@ static int sienna_cichlid_get_power_limit(struct smu_context *smu, 
		*default_power_limit = power_limit;



	if (powerplay_table) {

		if (smu->od_enabled)

		if (smu->od_enabled &&

				sienna_cichlid_is_od_feature_supported(od_settings, SMU_11_0_7_ODCAP_POWER_LIMIT)) {

			od_percent_upper = le32_to_cpu(powerplay_table->overdrive_table.max[SMU_11_0_7_ODSETTING_POWERPERCENTAGE]);

		else

			od_percent_lower = le32_to_cpu(powerplay_table->overdrive_table.min[SMU_11_0_7_ODSETTING_POWERPERCENTAGE]);

		} else if ((sienna_cichlid_is_od_feature_supported(od_settings, SMU_11_0_7_ODCAP_POWER_LIMIT))) {

			od_percent_upper = 0;



			od_percent_lower = le32_to_cpu(powerplay_table->overdrive_table.min[SMU_11_0_7_ODSETTING_POWERPERCENTAGE]);

		}

	}



	dev_dbg(smu->adev->dev, "od percent upper:%d, od percent lower:%d (default power: %d)\n",

					od_percent_upper, od_percent_lower, power_limit);
@@ -1252,12 +1261,6 @@ static bool sienna_cichlid_is_support_fine_grained_dpm(struct smu_context *smu, 
	return dpm_desc->SnapToDiscrete == 0;

}



static bool sienna_cichlid_is_od_feature_supported(struct smu_11_0_7_overdrive_table *od_table,

						   enum SMU_11_0_7_ODFEATURE_CAP cap)

{

	return od_table->cap[cap];

}



static void sienna_cichlid_get_od_setting_range(struct smu_11_0_7_overdrive_table *od_table,

						enum SMU_11_0_7_ODSETTING_ID setting,

						uint32_t *min, uint32_t *max)

drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c

+6 −4
Original line number Diff line number Diff line
@@ -2370,13 +2370,15 @@ static int smu_v13_0_0_get_power_limit(struct smu_context *smu, 
		*default_power_limit = power_limit;



	if (powerplay_table) {

		if (smu->od_enabled)

		if (smu->od_enabled &&

				smu_v13_0_0_is_od_feature_supported(smu, PP_OD_FEATURE_PPT_BIT)) {

			od_percent_upper = le32_to_cpu(powerplay_table->overdrive_table.max[SMU_13_0_0_ODSETTING_POWERPERCENTAGE]);

		else

			od_percent_lower = le32_to_cpu(powerplay_table->overdrive_table.min[SMU_13_0_0_ODSETTING_POWERPERCENTAGE]);

		} else if (smu_v13_0_0_is_od_feature_supported(smu, PP_OD_FEATURE_PPT_BIT)) {

			od_percent_upper = 0;



			od_percent_lower = le32_to_cpu(powerplay_table->overdrive_table.min[SMU_13_0_0_ODSETTING_POWERPERCENTAGE]);

		}

	}



	dev_dbg(smu->adev->dev, "od percent upper:%d, od percent lower:%d (default power: %d)\n",

					od_percent_upper, od_percent_lower, power_limit);

drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_7_ppt.c

+6 −4
Original line number Diff line number Diff line
@@ -2334,13 +2334,15 @@ static int smu_v13_0_7_get_power_limit(struct smu_context *smu, 
		*default_power_limit = power_limit;



	if (powerplay_table) {

		if (smu->od_enabled)

		if (smu->od_enabled &&

				(smu_v13_0_7_is_od_feature_supported(smu, PP_OD_FEATURE_PPT_BIT))) {

			od_percent_upper = le32_to_cpu(powerplay_table->overdrive_table.max[SMU_13_0_7_ODSETTING_POWERPERCENTAGE]);

		else

			od_percent_lower = le32_to_cpu(powerplay_table->overdrive_table.min[SMU_13_0_7_ODSETTING_POWERPERCENTAGE]);

		} else if (smu_v13_0_7_is_od_feature_supported(smu, PP_OD_FEATURE_PPT_BIT)) {

			od_percent_upper = 0;



			od_percent_lower = le32_to_cpu(powerplay_table->overdrive_table.min[SMU_13_0_7_ODSETTING_POWERPERCENTAGE]);

		}

	}



	dev_dbg(smu->adev->dev, "od percent upper:%d, od percent lower:%d (default power: %d)\n",

					od_percent_upper, od_percent_lower, power_limit);