Commit e18c09b2 authored by Jinqian Yang's avatar Jinqian Yang Committed by Catalin Marinas
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arm64: Add support for HIP09 Spectre-BHB mitigation 



The HIP09 processor is vulnerable to the Spectre-BHB (Branch History
Buffer) attack, which can be exploited to leak information through
branch prediction side channels. This commit adds the MIDR of HIP09
to the list for software mitigation.

Signed-off-by: default avatarJinqian Yang <yangjinqian1@huawei.com>
Link: https://lore.kernel.org/r/20250325141900.2057314-1-yangjinqian1@huawei.com


Signed-off-by: default avatarCatalin Marinas <catalin.marinas@arm.com>
parent 0fff2aa9

arch/arm64/include/asm/cputype.h

+2 −0
Original line number Diff line number Diff line
@@ -132,6 +132,7 @@ 
#define FUJITSU_CPU_PART_A64FX		0x001



#define HISI_CPU_PART_TSV110		0xD01

#define HISI_CPU_PART_HIP09			0xD02



#define APPLE_CPU_PART_M1_ICESTORM	0x022

#define APPLE_CPU_PART_M1_FIRESTORM	0x023
@@ -218,6 +219,7 @@ 
#define MIDR_NVIDIA_CARMEL MIDR_CPU_MODEL(ARM_CPU_IMP_NVIDIA, NVIDIA_CPU_PART_CARMEL)

#define MIDR_FUJITSU_A64FX MIDR_CPU_MODEL(ARM_CPU_IMP_FUJITSU, FUJITSU_CPU_PART_A64FX)

#define MIDR_HISI_TSV110 MIDR_CPU_MODEL(ARM_CPU_IMP_HISI, HISI_CPU_PART_TSV110)

#define MIDR_HISI_HIP09 MIDR_CPU_MODEL(ARM_CPU_IMP_HISI, HISI_CPU_PART_HIP09)

#define MIDR_APPLE_M1_ICESTORM MIDR_CPU_MODEL(ARM_CPU_IMP_APPLE, APPLE_CPU_PART_M1_ICESTORM)

#define MIDR_APPLE_M1_FIRESTORM MIDR_CPU_MODEL(ARM_CPU_IMP_APPLE, APPLE_CPU_PART_M1_FIRESTORM)

#define MIDR_APPLE_M1_ICESTORM_PRO MIDR_CPU_MODEL(ARM_CPU_IMP_APPLE, APPLE_CPU_PART_M1_ICESTORM_PRO)

arch/arm64/kernel/proton-pack.c

+1 −0
Original line number Diff line number Diff line
@@ -901,6 +901,7 @@ static u8 spectre_bhb_loop_affected(void) 
		MIDR_ALL_VERSIONS(MIDR_CORTEX_A77),

		MIDR_ALL_VERSIONS(MIDR_NEOVERSE_N1),

		MIDR_ALL_VERSIONS(MIDR_QCOM_KRYO_4XX_GOLD),

		MIDR_ALL_VERSIONS(MIDR_HISI_HIP09),

		{},

	};

	static const struct midr_range spectre_bhb_k11_list[] = {