Commit e1cb67ab authored by Konrad Dybcio's avatar Konrad Dybcio Committed by Manivannan Sadhasivam
Browse files

dt-bindings: PCI: qcom,pcie-sm8150: Drop unrelated clocks from PCIe hosts 



The TBU clock belongs to the Translation Buffer Unit, part of the SMMU.
The ref clock is already being driven upstream through some of the
branches.

Signed-off-by: default avatarKonrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Signed-off-by: default avatarManivannan Sadhasivam <mani@kernel.org>
Acked-by: default avatarRob Herring (Arm) <robh@kernel.org>
Link: https://patch.msgid.link/20250521-topic-8150_pcie_drop_clocks-v1-2-3d42e84f6453@oss.qualcomm.com
parent 26daa18e

Documentation/devicetree/bindings/pci/qcom,pcie-sm8150.yaml

+4 −10
Original line number Diff line number Diff line
@@ -38,8 +38,8 @@ properties: 
      - const: mhi # MHI registers



  clocks:

    minItems: 8

    maxItems: 8

    minItems: 6

    maxItems: 6



  clock-names:

    items:
@@ -49,8 +49,6 @@ properties: 
      - const: bus_master # Master AXI clock

      - const: bus_slave # Slave AXI clock

      - const: slave_q2a # Slave Q2A clock

      - const: tbu # PCIe TBU clock

      - const: ref # REFERENCE clock



  interrupts:

    minItems: 8
@@ -116,17 +114,13 @@ examples: 
                     <&gcc GCC_PCIE_0_CFG_AHB_CLK>,

                     <&gcc GCC_PCIE_0_MSTR_AXI_CLK>,

                     <&gcc GCC_PCIE_0_SLV_AXI_CLK>,

                     <&gcc GCC_PCIE_0_SLV_Q2A_AXI_CLK>,

                     <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>,

                     <&rpmhcc RPMH_CXO_CLK>;

                     <&gcc GCC_PCIE_0_SLV_Q2A_AXI_CLK>;

            clock-names = "pipe",

                          "aux",

                          "cfg",

                          "bus_master",

                          "bus_slave",

                          "slave_q2a",

                          "tbu",

                          "ref";

                          "slave_q2a";



            interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>,

                         <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,