Commit e1e6b571 authored by Ahmed S. Darwish's avatar Ahmed S. Darwish Committed by Ingo Molnar
Browse files

x86/cacheinfo: Use enums for cache descriptor types 



The leaf 0x2 one-byte cache descriptor types:

	CACHE_L1_INST
	CACHE_L1_DATA
	CACHE_L2
	CACHE_L3

are just discriminators to be used within the cache_table[] mapping.
Their specific values are irrelevant.

Use enums for such types.

Make the enum packed and static assert that its values remain within a
single byte so that the cache_table[] array size do not go out of hand.

Use a __CHECKER__ guard for the static_assert(sizeof(enum) == 1) line as
sparse ignores the __packed annotation on enums.

This is similar to:

  fe3944fb ("fs: Move enum rw_hint into a new header file")

for the core SCSI code.

Signed-off-by: default avatarAhmed S. Darwish <darwi@linutronix.de>
Signed-off-by: default avatarIngo Molnar <mingo@kernel.org>
Cc: H. Peter Anvin <hpa@zytor.com>
Cc: Linus Torvalds <torvalds@linux-foundation.org>
Link: https://lore.kernel.org/r/Z9rsTirs9lLfEPD9@lx-t490
Link: https://lore.kernel.org/r/20250324133324.23458-19-darwi@linutronix.de
parent 7596ab7a

arch/x86/include/asm/cpuid/types.h

+15 −0
Original line number Diff line number Diff line
@@ -2,6 +2,7 @@ 
#ifndef _ASM_X86_CPUID_TYPES_H

#define _ASM_X86_CPUID_TYPES_H



#include <linux/build_bug.h>

#include <linux/types.h>



/*
@@ -45,4 +46,18 @@ union leaf_0x2_regs { 
	u8			desc[16];

};



/*

 * Leaf 0x2 1-byte descriptors' cache types

 * To be used for their mappings at cache_table[]

 */

enum _cache_table_type {

	CACHE_L1_INST,

	CACHE_L1_DATA,

	CACHE_L2,

	CACHE_L3,

} __packed;

#ifndef __CHECKER__

static_assert(sizeof(enum _cache_table_type) == 1);

#endif



#endif /* _ASM_X86_CPUID_TYPES_H */

arch/x86/kernel/cpu/cacheinfo.c

+2 −7
Original line number Diff line number Diff line
@@ -23,11 +23,6 @@ 


#include "cpu.h"



#define CACHE_L1_INST	1

#define CACHE_L1_DATA	2

#define CACHE_L2	3

#define CACHE_L3	4



/* Shared last level cache maps */

DEFINE_PER_CPU_READ_MOSTLY(cpumask_var_t, cpu_llc_shared_map);
@@ -41,7 +36,7 @@ unsigned int memory_caching_control __ro_after_init; 


struct _cache_table {

	u8 descriptor;

	char cache_type;

	enum _cache_table_type type;

	short size;

};
@@ -520,7 +515,7 @@ void init_intel_cacheinfo(struct cpuinfo_x86 *c) 
			if (!entry)

				continue;



			switch (entry->cache_type) {

			switch (entry->type) {

			case CACHE_L1_INST:	l1i += entry->size; break;

			case CACHE_L1_DATA:	l1d += entry->size; break;

			case CACHE_L2:		l2  += entry->size; break;