Commit e208f83a authored by Mike Frysinger's avatar Mike Frysinger Committed by Bryan Wu
Browse files

Blackfin arch: use HI/LO macros rather than masking the bit ranges ourselves 



Signed-off-by: default avatarMike Frysinger <michael.frysinger@analog.com>
Signed-off-by: default avatarBryan Wu <bryan.wu@analog.com>
parent 36a1548f

arch/blackfin/mach-bf533/head.S

+6 −6
Original line number Diff line number Diff line
@@ -144,8 +144,8 @@ ENTRY(__start) 
	ssync;



	/* Turn off the icache */

	p0.l = (IMEM_CONTROL & 0xFFFF);

	p0.h = (IMEM_CONTROL >> 16);

	p0.l = LO(IMEM_CONTROL);

	p0.h = HI(IMEM_CONTROL);

	R1 = [p0];

	R0 = ~ENICPLB;

	R0 = R0 & R1;
@@ -162,8 +162,8 @@ ENTRY(__start) 
#endif



	/* Turn off the dcache */

	p0.l = (DMEM_CONTROL & 0xFFFF);

	p0.h = (DMEM_CONTROL >> 16);

	p0.l = LO(DMEM_CONTROL);

	p0.h = HI(DMEM_CONTROL);

	R1 = [p0];

	R0 = ~ENDCPLB;

	R0 = R0 & R1;
@@ -417,8 +417,8 @@ ENTRY(_start_dma_code) 
	w[p0] = r0.l;

	ssync;



	p0.l = (EBIU_SDBCTL & 0xFFFF);

	p0.h = (EBIU_SDBCTL >> 16);     /* SDRAM Memory Bank Control Register */

	p0.l = LO(EBIU_SDBCTL);

	p0.h = HI(EBIU_SDBCTL);     /* SDRAM Memory Bank Control Register */

	r0 = mem_SDBCTL;

	w[p0] = r0.l;

	ssync;

arch/blackfin/mach-bf537/head.S

+6 −6
Original line number Diff line number Diff line
@@ -100,8 +100,8 @@ ENTRY(__start) 
	R0 = R1;



	/* Turn off the icache */

	p0.l = (IMEM_CONTROL & 0xFFFF);

	p0.h = (IMEM_CONTROL >> 16);

	p0.l = LO(IMEM_CONTROL);

	p0.h = HI(IMEM_CONTROL);

	R1 = [p0];

	R0 = ~ENICPLB;

	R0 = R0 & R1;
@@ -118,8 +118,8 @@ ENTRY(__start) 
#endif



	/* Turn off the dcache */

	p0.l = (DMEM_CONTROL & 0xFFFF);

	p0.h = (DMEM_CONTROL >> 16);

	p0.l = LO(DMEM_CONTROL);

	p0.h = HI(DMEM_CONTROL);

	R1 = [p0];

	R0 = ~ENDCPLB;

	R0 = R0 & R1;
@@ -436,8 +436,8 @@ ENTRY(_start_dma_code) 
	w[p0] = r0.l;

	ssync;



	p0.l = (EBIU_SDBCTL & 0xFFFF);

	p0.h = (EBIU_SDBCTL >> 16);     /* SDRAM Memory Bank Control Register */

	p0.l = LO(EBIU_SDBCTL);

	p0.h = HI(EBIU_SDBCTL);     /* SDRAM Memory Bank Control Register */

	r0 = mem_SDBCTL;

	w[p0] = r0.l;

	ssync;

arch/blackfin/mach-bf548/head.S

+6 −6
Original line number Diff line number Diff line
@@ -97,8 +97,8 @@ ENTRY(__stext) 
	R0 = R1;



	/* Turn off the icache */

	p0.l = (IMEM_CONTROL & 0xFFFF);

	p0.h = (IMEM_CONTROL >> 16);

	p0.l = LO(IMEM_CONTROL);

	p0.h = HI(IMEM_CONTROL);

	R1 = [p0];

	R0 = ~ENICPLB;

	R0 = R0 & R1;
@@ -106,8 +106,8 @@ ENTRY(__stext) 
	SSYNC;



	/* Turn off the dcache */

	p0.l = (DMEM_CONTROL & 0xFFFF);

	p0.h = (DMEM_CONTROL >> 16);

	p0.l = LO(DMEM_CONTROL);

	p0.h = HI(DMEM_CONTROL);

	R1 = [p0];

	R0 = ~ENDCPLB;

	R0 = R0 & R1;
@@ -335,8 +335,8 @@ ENTRY(_start_dma_code) 
	w[p0] = r0.l;

	ssync;



	p0.l = (EBIU_SDBCTL & 0xFFFF);

	p0.h = (EBIU_SDBCTL >> 16);     /* SDRAM Memory Bank Control Register */

	p0.l = LO(EBIU_SDBCTL);

	p0.h = HI(EBIU_SDBCTL);     /* SDRAM Memory Bank Control Register */

	r0 = mem_SDBCTL;

	w[p0] = r0.l;

	ssync;

arch/blackfin/mach-bf561/head.S

+6 −6
Original line number Diff line number Diff line
@@ -100,8 +100,8 @@ ENTRY(__start) 
	R0 = R1;



	/* Turn off the icache */

	p0.l = (IMEM_CONTROL & 0xFFFF);

	p0.h = (IMEM_CONTROL >> 16);

	p0.l = LO(IMEM_CONTROL);

	p0.h = HI(IMEM_CONTROL);

	R1 = [p0];

	R0 = ~ENICPLB;

	R0 = R0 & R1;
@@ -117,8 +117,8 @@ ENTRY(__start) 
#endif



	/* Turn off the dcache */

	p0.l = (DMEM_CONTROL & 0xFFFF);

	p0.h = (DMEM_CONTROL >> 16);

	p0.l = LO(DMEM_CONTROL);

	p0.h = HI(DMEM_CONTROL);

	R1 = [p0];

	R0 = ~ENDCPLB;

	R0 = R0 & R1;
@@ -371,8 +371,8 @@ ENTRY(_start_dma_code) 
	w[p0] = r0.l;

	ssync;



	p0.l = (EBIU_SDBCTL & 0xFFFF);

	p0.h = (EBIU_SDBCTL >> 16);     /* SDRAM Memory Bank Control Register */

	p0.l = LO(EBIU_SDBCTL);

	p0.h = HI(EBIU_SDBCTL);     /* SDRAM Memory Bank Control Register */

	r0 = mem_SDBCTL;

	w[p0] = r0.l;

	ssync;

arch/blackfin/mach-common/cache.S

+4 −4
Original line number Diff line number Diff line
@@ -79,8 +79,8 @@ ENTRY(_icache_invalidate) 
ENTRY(_invalidate_entire_icache)

	[--SP] = ( R7:5);



	P0.L = (IMEM_CONTROL & 0xFFFF);

	P0.H = (IMEM_CONTROL >> 16);

	P0.L = LO(IMEM_CONTROL);

	P0.H = HI(IMEM_CONTROL);

	R7 = [P0];



	/* Clear the IMC bit , All valid bits in the instruction
@@ -197,8 +197,8 @@ ENTRY(_invalidate_entire_dcache) 
ENTRY(_dcache_invalidate)

	[--SP] = ( R7:6);



	P0.L = (DMEM_CONTROL & 0xFFFF);

	P0.H = (DMEM_CONTROL >> 16);

	P0.L = LO(DMEM_CONTROL);

	P0.H = HI(DMEM_CONTROL);

	R7 = [P0];



	/* Clear the DMC[1:0] bits, All valid bits in the data