perf vendor events: Add/update skylake events/metrics (e2641db8) · Commits · git / linux-net

tools/perf/pmu-events/arch/x86/mapfile.csv

+1 −1

Original line number	Diff line number	Diff line
		@@ -29,7 +29,7 @@ GenuineIntel-6-2A,v19,sandybridge,core
		GenuineIntel-6-8F,v1.23,sapphirerapids,core
		GenuineIntel-6-AF,v1.04,sierraforest,core
		GenuineIntel-6-(37\|4A\|4C\|4D\|5A),v15,silvermont,core
		GenuineIntel-6-(4E\|5E\|8E\|9E\|A5\|A6),v58,skylake,core
		GenuineIntel-6-(4E\|5E\|8E\|9E\|A5\|A6),v59,skylake,core
		GenuineIntel-6-55-[01234],v1.33,skylakex,core
		GenuineIntel-6-86,v1.22,snowridgex,core
		GenuineIntel-6-8[CD],v1.15,tigerlake,core

tools/perf/pmu-events/arch/x86/skylake/cache.json

+250 −0

File changed.

Preview size limit exceeded, changes collapsed.

tools/perf/pmu-events/arch/x86/skylake/counter.json

0 → 100644

+22 −0

Original line number	Diff line number	Diff line
		[
		{
		"Unit": "core",
		"CountersNumFixed": "3",
		"CountersNumGeneric": "4"
		},
		{
		"Unit": "CBOX",
		"CountersNumFixed": "0",
		"CountersNumGeneric": "2"
		},
		{
		"Unit": "ARB",
		"CountersNumFixed": "0",
		"CountersNumGeneric": "2"
		},
		{
		"Unit": "cbox_0",
		"CountersNumFixed": 1,
		"CountersNumGeneric": "0"
		}
		]
		No newline at end of file

tools/perf/pmu-events/arch/x86/skylake/floating-point.json

+10 −0

Original line number	Diff line number	Diff line
		[
		{
		"BriefDescription": "Counts once for most SIMD 128-bit packed computational double precision floating-point instructions retired. Counts twice for DPP and FM(N)ADD/SUB instructions retired.",
		"Counter": "0,1,2,3",
		"EventCode": "0xC7",
		"EventName": "FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE",
		"PublicDescription": "Counts once for most SIMD 128-bit packed computational double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 2 computation operations, one for each element. Applies to packed double precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.",
		@@ -9,6 +10,7 @@
		},
		{
		"BriefDescription": "Counts once for most SIMD 128-bit packed computational single precision floating-point instruction retired. Counts twice for DPP and FM(N)ADD/SUB instructions retired.",
		"Counter": "0,1,2,3",
		"EventCode": "0xC7",
		"EventName": "FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE",
		"PublicDescription": "Counts once for most SIMD 128-bit packed computational single precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 4 computation operations, one for each element. Applies to packed single precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT RSQRT RCP DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.",
		@@ -17,6 +19,7 @@
		},
		{
		"BriefDescription": "Counts once for most SIMD 256-bit packed double computational precision floating-point instructions retired. Counts twice for DPP and FM(N)ADD/SUB instructions retired.",
		"Counter": "0,1,2,3",
		"EventCode": "0xC7",
		"EventName": "FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE",
		"PublicDescription": "Counts once for most SIMD 256-bit packed double computational precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 4 computation operations, one for each element. Applies to packed double precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.",
		@@ -25,6 +28,7 @@
		},
		{
		"BriefDescription": "Counts once for most SIMD 256-bit packed single computational precision floating-point instructions retired. Counts twice for DPP and FM(N)ADD/SUB instructions retired.",
		"Counter": "0,1,2,3",
		"EventCode": "0xC7",
		"EventName": "FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE",
		"PublicDescription": "Counts once for most SIMD 256-bit packed single computational precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 8 computation operations, one for each element. Applies to packed single precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT RSQRT RCP DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.",
		@@ -33,6 +37,7 @@
		},
		{
		"BriefDescription": "Number of SSE/AVX computational 128-bit packed single and 256-bit packed double precision FP instructions retired; some instructions will count twice as noted below. Each count represents 2 or/and 4 computation operations, 1 for each element. Applies to SSE* and AVX* packed single precision and packed double precision FP instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX RCP14 RSQRT14 SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB count twice as they perform 2 calculations per element.",
		"Counter": "0,1,2,3",
		"EventCode": "0xC7",
		"EventName": "FP_ARITH_INST_RETIRED.4_FLOPS",
		"PublicDescription": "Number of SSE/AVX computational 128-bit packed single precision and 256-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 2 or/and 4 computation operations, one for each element. Applies to SSE* and AVX* packed single precision floating-point and packed double precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX RCP14 RSQRT14 SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.",
		@@ -41,6 +46,7 @@
		},
		{
		"BriefDescription": "Counts once for most SIMD scalar computational floating-point instructions retired. Counts twice for DPP and FM(N)ADD/SUB instructions retired.",
		"Counter": "0,1,2,3",
		"EventCode": "0xC7",
		"EventName": "FP_ARITH_INST_RETIRED.SCALAR",
		"PublicDescription": "Counts once for most SIMD scalar computational single precision and double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 1 computational operation. Applies to SIMD scalar single precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT RSQRT RCP FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.",
		@@ -49,6 +55,7 @@
		},
		{
		"BriefDescription": "Counts once for most SIMD scalar computational double precision floating-point instructions retired. Counts twice for DPP and FM(N)ADD/SUB instructions retired.",
		"Counter": "0,1,2,3",
		"EventCode": "0xC7",
		"EventName": "FP_ARITH_INST_RETIRED.SCALAR_DOUBLE",
		"PublicDescription": "Counts once for most SIMD scalar computational double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 1 computational operation. Applies to SIMD scalar double precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.",
		@@ -57,6 +64,7 @@
		},
		{
		"BriefDescription": "Counts once for most SIMD scalar computational single precision floating-point instructions retired. Counts twice for DPP and FM(N)ADD/SUB instructions retired.",
		"Counter": "0,1,2,3",
		"EventCode": "0xC7",
		"EventName": "FP_ARITH_INST_RETIRED.SCALAR_SINGLE",
		"PublicDescription": "Counts once for most SIMD scalar computational single precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 1 computational operation. Applies to SIMD scalar single precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT RSQRT RCP FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.",
		@@ -65,6 +73,7 @@
		},
		{
		"BriefDescription": "Number of any Vector retired FP arithmetic instructions",
		"Counter": "0,1,2,3",
		"EventCode": "0xC7",
		"EventName": "FP_ARITH_INST_RETIRED.VECTOR",
		"SampleAfterValue": "2000003",
		@@ -72,6 +81,7 @@
		},
		{
		"BriefDescription": "Cycles with any input/output SSE or FP assist",
		"Counter": "0,1,2,3",
		"CounterMask": "1",
		"EventCode": "0xCA",
		"EventName": "FP_ASSIST.ANY",

tools/perf/pmu-events/arch/x86/skylake/frontend.json

+49 −0

Original line number	Diff line number	Diff line
		[
		{
		"BriefDescription": "Counts the total number when the front end is resteered, mainly when the BPU cannot provide a correct prediction and this is corrected by other branch handling mechanisms at the front end.",
		"Counter": "0,1,2,3",
		"EventCode": "0xE6",
		"EventName": "BACLEARS.ANY",
		"PublicDescription": "Counts the number of times the front-end is resteered when it finds a branch instruction in a fetch line. This occurs for the first time a branch instruction is fetched or when the branch is not tracked by the BPU (Branch Prediction Unit) anymore.",
		@@ -9,6 +10,7 @@
		},
		{
		"BriefDescription": "Stalls caused by changing prefix length of the instruction. [This event is alias to ILD_STALL.LCP]",
		"Counter": "0,1,2,3",
		"EventCode": "0x87",
		"EventName": "DECODE.LCP",
		"PublicDescription": "Counts cycles that the Instruction Length decoder (ILD) stalls occurred due to dynamically changing prefix length of the decoded instruction (by operand size prefix instruction 0x66, address size prefix instruction 0x67 or REX.W for Intel64). Count is proportional to the number of prefixes in a 16B-line. This may result in a three-cycle penalty for each LCP (Length changing prefix) in a 16-byte chunk. [This event is alias to ILD_STALL.LCP]",
		@@ -17,6 +19,7 @@
		},
		{
		"BriefDescription": "Decode Stream Buffer (DSB)-to-MITE switches",
		"Counter": "0,1,2,3",
		"EventCode": "0xAB",
		"EventName": "DSB2MITE_SWITCHES.COUNT",
		"PublicDescription": "This event counts the number of the Decode Stream Buffer (DSB)-to-MITE switches including all misses because of missing Decode Stream Buffer (DSB) cache and u-arch forced misses. Note: Invoking MITE requires two or three cycles delay.",
		@@ -25,6 +28,7 @@
		},
		{
		"BriefDescription": "Decode Stream Buffer (DSB)-to-MITE switch true penalty cycles.",
		"Counter": "0,1,2,3",
		"EventCode": "0xAB",
		"EventName": "DSB2MITE_SWITCHES.PENALTY_CYCLES",
		"PublicDescription": "Counts Decode Stream Buffer (DSB)-to-MITE switch true penalty cycles. These cycles do not include uops routed through because of the switch itself, for example, when Instruction Decode Queue (IDQ) pre-allocation is unavailable, or Instruction Decode Queue (IDQ) is full. SBD-to-MITE switch true penalty cycles happen after the merge mux (MM) receives Decode Stream Buffer (DSB) Sync-indication until receiving the first MITE uop. MM is placed before Instruction Decode Queue (IDQ) to merge uops being fed from the MITE and Decode Stream Buffer (DSB) paths. Decode Stream Buffer (DSB) inserts the Sync-indication whenever a Decode Stream Buffer (DSB)-to-MITE switch occurs.Penalty: A Decode Stream Buffer (DSB) hit followed by a Decode Stream Buffer (DSB) miss can cost up to six cycles in which no uops are delivered to the IDQ. Most often, such switches from the Decode Stream Buffer (DSB) to the legacy pipeline cost 02 cycles.",
		@@ -33,6 +37,7 @@
		},
		{
		"BriefDescription": "Retired Instructions who experienced DSB miss.",
		"Counter": "0,1,2,3",
		"EventCode": "0xC6",
		"EventName": "FRONTEND_RETIRED.ANY_DSB_MISS",
		"MSRIndex": "0x3F7",
		@@ -44,6 +49,7 @@
		},
		{
		"BriefDescription": "Retired Instructions who experienced a critical DSB miss.",
		"Counter": "0,1,2,3",
		"EventCode": "0xC6",
		"EventName": "FRONTEND_RETIRED.DSB_MISS",
		"MSRIndex": "0x3F7",
		@@ -55,6 +61,7 @@
		},
		{
		"BriefDescription": "Retired Instructions who experienced iTLB true miss.",
		"Counter": "0,1,2,3",
		"EventCode": "0xC6",
		"EventName": "FRONTEND_RETIRED.ITLB_MISS",
		"MSRIndex": "0x3F7",
		@@ -66,6 +73,7 @@
		},
		{
		"BriefDescription": "Retired Instructions who experienced Instruction L1 Cache true miss.",
		"Counter": "0,1,2,3",
		"EventCode": "0xC6",
		"EventName": "FRONTEND_RETIRED.L1I_MISS",
		"MSRIndex": "0x3F7",
		@@ -76,6 +84,7 @@
		},
		{
		"BriefDescription": "Retired Instructions who experienced Instruction L2 Cache true miss.",
		"Counter": "0,1,2,3",
		"EventCode": "0xC6",
		"EventName": "FRONTEND_RETIRED.L2_MISS",
		"MSRIndex": "0x3F7",
		@@ -86,6 +95,7 @@
		},
		{
		"BriefDescription": "Retired instructions after front-end starvation of at least 1 cycle",
		"Counter": "0,1,2,3",
		"EventCode": "0xc6",
		"EventName": "FRONTEND_RETIRED.LATENCY_GE_1",
		"MSRIndex": "0x3F7",
		@@ -97,6 +107,7 @@
		},
		{
		"BriefDescription": "Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 128 cycles which was not interrupted by a back-end stall.",
		"Counter": "0,1,2,3",
		"EventCode": "0xC6",
		"EventName": "FRONTEND_RETIRED.LATENCY_GE_128",
		"MSRIndex": "0x3F7",
		@@ -107,6 +118,7 @@
		},
		{
		"BriefDescription": "Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 16 cycles which was not interrupted by a back-end stall.",
		"Counter": "0,1,2,3",
		"EventCode": "0xC6",
		"EventName": "FRONTEND_RETIRED.LATENCY_GE_16",
		"MSRIndex": "0x3F7",
		@@ -118,6 +130,7 @@
		},
		{
		"BriefDescription": "Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 2 cycles which was not interrupted by a back-end stall.",
		"Counter": "0,1,2,3",
		"EventCode": "0xC6",
		"EventName": "FRONTEND_RETIRED.LATENCY_GE_2",
		"MSRIndex": "0x3F7",
		@@ -128,6 +141,7 @@
		},
		{
		"BriefDescription": "Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 256 cycles which was not interrupted by a back-end stall.",
		"Counter": "0,1,2,3",
		"EventCode": "0xC6",
		"EventName": "FRONTEND_RETIRED.LATENCY_GE_256",
		"MSRIndex": "0x3F7",
		@@ -138,6 +152,7 @@
		},
		{
		"BriefDescription": "Retired instructions that are fetched after an interval where the front-end had at least 1 bubble-slot for a period of 2 cycles which was not interrupted by a back-end stall.",
		"Counter": "0,1,2,3",
		"EventCode": "0xC6",
		"EventName": "FRONTEND_RETIRED.LATENCY_GE_2_BUBBLES_GE_1",
		"MSRIndex": "0x3F7",
		@@ -149,6 +164,7 @@
		},
		{
		"BriefDescription": "Retired instructions that are fetched after an interval where the front-end had at least 2 bubble-slots for a period of 2 cycles which was not interrupted by a back-end stall.",
		"Counter": "0,1,2,3",
		"EventCode": "0xC6",
		"EventName": "FRONTEND_RETIRED.LATENCY_GE_2_BUBBLES_GE_2",
		"MSRIndex": "0x3F7",
		@@ -159,6 +175,7 @@
		},
		{
		"BriefDescription": "Retired instructions that are fetched after an interval where the front-end had at least 3 bubble-slots for a period of 2 cycles which was not interrupted by a back-end stall.",
		"Counter": "0,1,2,3",
		"EventCode": "0xC6",
		"EventName": "FRONTEND_RETIRED.LATENCY_GE_2_BUBBLES_GE_3",
		"MSRIndex": "0x3F7",
		@@ -169,6 +186,7 @@
		},
		{
		"BriefDescription": "Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 32 cycles which was not interrupted by a back-end stall.",
		"Counter": "0,1,2,3",
		"EventCode": "0xC6",
		"EventName": "FRONTEND_RETIRED.LATENCY_GE_32",
		"MSRIndex": "0x3F7",
		@@ -180,6 +198,7 @@
		},
		{
		"BriefDescription": "Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 4 cycles which was not interrupted by a back-end stall.",
		"Counter": "0,1,2,3",
		"EventCode": "0xC6",
		"EventName": "FRONTEND_RETIRED.LATENCY_GE_4",
		"MSRIndex": "0x3F7",
		@@ -190,6 +209,7 @@
		},
		{
		"BriefDescription": "Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 512 cycles which was not interrupted by a back-end stall.",
		"Counter": "0,1,2,3",
		"EventCode": "0xC6",
		"EventName": "FRONTEND_RETIRED.LATENCY_GE_512",
		"MSRIndex": "0x3F7",
		@@ -200,6 +220,7 @@
		},
		{
		"BriefDescription": "Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 64 cycles which was not interrupted by a back-end stall.",
		"Counter": "0,1,2,3",
		"EventCode": "0xC6",
		"EventName": "FRONTEND_RETIRED.LATENCY_GE_64",
		"MSRIndex": "0x3F7",
		@@ -210,6 +231,7 @@
		},
		{
		"BriefDescription": "Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 8 cycles which was not interrupted by a back-end stall.",
		"Counter": "0,1,2,3",
		"EventCode": "0xC6",
		"EventName": "FRONTEND_RETIRED.LATENCY_GE_8",
		"MSRIndex": "0x3F7",
		@@ -221,6 +243,7 @@
		},
		{
		"BriefDescription": "Retired Instructions who experienced STLB (2nd level TLB) true miss.",
		"Counter": "0,1,2,3",
		"EventCode": "0xC6",
		"EventName": "FRONTEND_RETIRED.STLB_MISS",
		"MSRIndex": "0x3F7",
		@@ -232,6 +255,7 @@
		},
		{
		"BriefDescription": "Cycles where a code fetch is stalled due to L1 instruction cache miss.",
		"Counter": "0,1,2,3",
		"EventCode": "0x80",
		"EventName": "ICACHE_16B.IFDATA_STALL",
		"PublicDescription": "Cycles where a code line fetch is stalled due to an L1 instruction cache miss. The legacy decode pipeline works at a 16 Byte granularity.",
		@@ -240,6 +264,7 @@
		},
		{
		"BriefDescription": "Instruction fetch tag lookups that hit in the instruction cache (L1I). Counts at 64-byte cache-line granularity.",
		"Counter": "0,1,2,3",
		"EventCode": "0x83",
		"EventName": "ICACHE_64B.IFTAG_HIT",
		"SampleAfterValue": "200003",
		@@ -247,6 +272,7 @@
		},
		{
		"BriefDescription": "Instruction fetch tag lookups that miss in the instruction cache (L1I). Counts at 64-byte cache-line granularity.",
		"Counter": "0,1,2,3",
		"EventCode": "0x83",
		"EventName": "ICACHE_64B.IFTAG_MISS",
		"SampleAfterValue": "200003",
		@@ -254,6 +280,7 @@
		},
		{
		"BriefDescription": "Cycles where a code fetch is stalled due to L1 instruction cache tag miss. [This event is alias to ICACHE_TAG.STALLS]",
		"Counter": "0,1,2,3",
		"EventCode": "0x83",
		"EventName": "ICACHE_64B.IFTAG_STALL",
		"SampleAfterValue": "200003",
		@@ -261,6 +288,7 @@
		},
		{
		"BriefDescription": "Cycles where a code fetch is stalled due to L1 instruction cache tag miss. [This event is alias to ICACHE_64B.IFTAG_STALL]",
		"Counter": "0,1,2,3",
		"EventCode": "0x83",
		"EventName": "ICACHE_TAG.STALLS",
		"SampleAfterValue": "200003",
		@@ -268,6 +296,7 @@
		},
		{
		"BriefDescription": "Cycles Decode Stream Buffer (DSB) is delivering 4 or more Uops [This event is alias to IDQ.DSB_CYCLES_OK]",
		"Counter": "0,1,2,3",
		"CounterMask": "4",
		"EventCode": "0x79",
		"EventName": "IDQ.ALL_DSB_CYCLES_4_UOPS",
		@@ -277,6 +306,7 @@
		},
		{
		"BriefDescription": "Cycles Decode Stream Buffer (DSB) is delivering any Uop [This event is alias to IDQ.DSB_CYCLES_ANY]",
		"Counter": "0,1,2,3",
		"CounterMask": "1",
		"EventCode": "0x79",
		"EventName": "IDQ.ALL_DSB_CYCLES_ANY_UOPS",
		@@ -286,6 +316,7 @@
		},
		{
		"BriefDescription": "Cycles MITE is delivering 4 Uops",
		"Counter": "0,1,2,3",
		"CounterMask": "4",
		"EventCode": "0x79",
		"EventName": "IDQ.ALL_MITE_CYCLES_4_UOPS",
		@@ -295,6 +326,7 @@
		},
		{
		"BriefDescription": "Cycles MITE is delivering any Uop",
		"Counter": "0,1,2,3",
		"CounterMask": "1",
		"EventCode": "0x79",
		"EventName": "IDQ.ALL_MITE_CYCLES_ANY_UOPS",
		@@ -304,6 +336,7 @@
		},
		{
		"BriefDescription": "Cycles when uops are being delivered to Instruction Decode Queue (IDQ) from Decode Stream Buffer (DSB) path",
		"Counter": "0,1,2,3",
		"CounterMask": "1",
		"EventCode": "0x79",
		"EventName": "IDQ.DSB_CYCLES",
		@@ -313,6 +346,7 @@
		},
		{
		"BriefDescription": "Cycles Decode Stream Buffer (DSB) is delivering any Uop [This event is alias to IDQ.ALL_DSB_CYCLES_ANY_UOPS]",
		"Counter": "0,1,2,3",
		"CounterMask": "1",
		"EventCode": "0x79",
		"EventName": "IDQ.DSB_CYCLES_ANY",
		@@ -322,6 +356,7 @@
		},
		{
		"BriefDescription": "Cycles Decode Stream Buffer (DSB) is delivering 4 or more Uops [This event is alias to IDQ.ALL_DSB_CYCLES_4_UOPS]",
		"Counter": "0,1,2,3",
		"CounterMask": "4",
		"EventCode": "0x79",
		"EventName": "IDQ.DSB_CYCLES_OK",
		@@ -331,6 +366,7 @@
		},
		{
		"BriefDescription": "Uops delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path",
		"Counter": "0,1,2,3",
		"EventCode": "0x79",
		"EventName": "IDQ.DSB_UOPS",
		"PublicDescription": "Counts the number of uops delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path. Counting includes uops that may 'bypass' the IDQ.",
		@@ -339,6 +375,7 @@
		},
		{
		"BriefDescription": "Cycles when uops are being delivered to Instruction Decode Queue (IDQ) from MITE path",
		"Counter": "0,1,2,3",
		"CounterMask": "1",
		"EventCode": "0x79",
		"EventName": "IDQ.MITE_CYCLES",
		@@ -348,6 +385,7 @@
		},
		{
		"BriefDescription": "Uops delivered to Instruction Decode Queue (IDQ) from MITE path",
		"Counter": "0,1,2,3",
		"EventCode": "0x79",
		"EventName": "IDQ.MITE_UOPS",
		"PublicDescription": "Counts the number of uops delivered to Instruction Decode Queue (IDQ) from the MITE path. Counting includes uops that may 'bypass' the IDQ. This also means that uops are not being delivered from the Decode Stream Buffer (DSB).",
		@@ -356,6 +394,7 @@
		},
		{
		"BriefDescription": "Cycles when uops are being delivered to Instruction Decode Queue (IDQ) while Microcode Sequencer (MS) is busy",
		"Counter": "0,1,2,3",
		"CounterMask": "1",
		"EventCode": "0x79",
		"EventName": "IDQ.MS_CYCLES",
		@@ -365,6 +404,7 @@
		},
		{
		"BriefDescription": "Cycles when uops initiated by Decode Stream Buffer (DSB) are being delivered to Instruction Decode Queue (IDQ) while Microcode Sequencer (MS) is busy",
		"Counter": "0,1,2,3",
		"CounterMask": "1",
		"EventCode": "0x79",
		"EventName": "IDQ.MS_DSB_CYCLES",
		@@ -374,6 +414,7 @@
		},
		{
		"BriefDescription": "Uops initiated by MITE and delivered to Instruction Decode Queue (IDQ) while Microcode Sequencer (MS) is busy",
		"Counter": "0,1,2,3",
		"EventCode": "0x79",
		"EventName": "IDQ.MS_MITE_UOPS",
		"PublicDescription": "Counts the number of uops initiated by MITE and delivered to Instruction Decode Queue (IDQ) while the Microcode Sequencer (MS) is busy. Counting includes uops that may 'bypass' the IDQ.",
		@@ -382,6 +423,7 @@
		},
		{
		"BriefDescription": "Number of switches from DSB (Decode Stream Buffer) or MITE (legacy decode pipeline) to the Microcode Sequencer",
		"Counter": "0,1,2,3",
		"CounterMask": "1",
		"EdgeDetect": "1",
		"EventCode": "0x79",
		@@ -392,6 +434,7 @@
		},
		{
		"BriefDescription": "Uops delivered to Instruction Decode Queue (IDQ) while Microcode Sequencer (MS) is busy",
		"Counter": "0,1,2,3",
		"EventCode": "0x79",
		"EventName": "IDQ.MS_UOPS",
		"PublicDescription": "Counts the total number of uops delivered by the Microcode Sequencer (MS). Any instruction over 4 uops will be delivered by the MS. Some instructions such as transcendentals may additionally generate uops from the MS.",
		@@ -400,6 +443,7 @@
		},
		{
		"BriefDescription": "Uops not delivered to Resource Allocation Table (RAT) per thread when backend of the machine is not stalled",
		"Counter": "0,1,2,3",
		"EventCode": "0x9C",
		"EventName": "IDQ_UOPS_NOT_DELIVERED.CORE",
		"PublicDescription": "Counts the number of uops not delivered to Resource Allocation Table (RAT) per thread adding 4 x when Resource Allocation Table (RAT) is not stalled and Instruction Decode Queue (IDQ) delivers x uops to Resource Allocation Table (RAT) (where x belongs to {0,1,2,3}). Counting does not cover cases when: a. IDQ-Resource Allocation Table (RAT) pipe serves the other thread. b. Resource Allocation Table (RAT) is stalled for the thread (including uop drops and clear BE conditions). c. Instruction Decode Queue (IDQ) delivers four uops.",
		@@ -408,6 +452,7 @@
		},
		{
		"BriefDescription": "Cycles per thread when 4 or more uops are not delivered to Resource Allocation Table (RAT) when backend of the machine is not stalled",
		"Counter": "0,1,2,3",
		"CounterMask": "4",
		"EventCode": "0x9C",
		"EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE",
		@@ -417,6 +462,7 @@
		},
		{
		"BriefDescription": "Counts cycles FE delivered 4 uops or Resource Allocation Table (RAT) was stalling FE.",
		"Counter": "0,1,2,3",
		"CounterMask": "1",
		"EventCode": "0x9C",
		"EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_FE_WAS_OK",
		@@ -426,6 +472,7 @@
		},
		{
		"BriefDescription": "Cycles per thread when 3 or more uops are not delivered to Resource Allocation Table (RAT) when backend of the machine is not stalled",
		"Counter": "0,1,2,3",
		"CounterMask": "3",
		"EventCode": "0x9C",
		"EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_LE_1_UOP_DELIV.CORE",
		@@ -435,6 +482,7 @@
		},
		{
		"BriefDescription": "Cycles with less than 2 uops delivered by the front end.",
		"Counter": "0,1,2,3",
		"CounterMask": "2",
		"EventCode": "0x9C",
		"EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_LE_2_UOP_DELIV.CORE",
		@@ -444,6 +492,7 @@
		},
		{
		"BriefDescription": "Cycles with less than 3 uops delivered by the front end.",
		"Counter": "0,1,2,3",
		"CounterMask": "1",
		"EventCode": "0x9C",
		"EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_LE_3_UOP_DELIV.CORE",