Commit e2692c4e authored by Wei Wang's avatar Wei Wang Committed by Joerg Roedel
Browse files

iommupt: Do not set C-bit on MMIO backed PTEs 



AMD Secure Memory Encryption (SME) marks individual memory pages as
encrypted by setting the C-bit in page table entries. According to the
AMD APM,any pages corresponding to MMIO addresses must be configured
with the C-bit clear.

The current *_iommu_set_prot() implementation sets the C-bit on all PTEs
in the IOMMU page tables. This is incorrect for PTEs backed by MMIO, and
can break PCIe peer-to-peer communication when IOVA is used. Fix this by
avoiding the C-bit for MMIO-backed mappings.

For amdv2 IOMMU page tables, there is a usage scenario for GVA->GPA
mappings, and for the trusted MMIO in the TEE-IO case, the C-bit will need
to be added to GPA. However, SNP guests do not yet support vIOMMU, and the
trusted MMIO support is not ready in upstream. Adding the C-bit for trusted
MMIO can be considered once those features land.

Fixes: 879ced2b ("iommupt: Add the AMD IOMMU v1 page table format")
Fixes: aef5de75 ("iommupt: Add the x86 64 bit page table format")
Suggested-by: default avatarJason Gunthorpe <jgg@nvidia.com>
Signed-off-by: default avatarWei Wang <wei.w.wang@hotmail.com>
Reviewed-by: default avatarJason Gunthorpe <jgg@nvidia.com>
Reviewed-by: default avatarKevin Tian <kevin.tian@intel.com>
Reviewed-by: default avatarVasant Hegde <vasant.hegde@amd.com>
Signed-off-by: default avatarJoerg Roedel <joerg.roedel@amd.com>
parent 16e3423f

drivers/iommu/generic_pt/fmt/amdv1.h

+2 −1
Original line number Diff line number Diff line
@@ -354,7 +354,8 @@ static inline int amdv1pt_iommu_set_prot(struct pt_common *common, 
	 * Ideally we'd have an IOMMU_ENCRYPTED flag set by higher levels to

	 * control this. For now if the tables use sme_set then so do the ptes.

	 */

	if (pt_feature(common, PT_FEAT_AMDV1_ENCRYPT_TABLES))

	if (pt_feature(common, PT_FEAT_AMDV1_ENCRYPT_TABLES) &&

	    !(iommu_prot & IOMMU_MMIO))

		pte = __sme_set(pte);



	attrs->descriptor_bits = pte;

drivers/iommu/generic_pt/fmt/x86_64.h

+2 −1
Original line number Diff line number Diff line
@@ -227,7 +227,8 @@ static inline int x86_64_pt_iommu_set_prot(struct pt_common *common, 
	 * Ideally we'd have an IOMMU_ENCRYPTED flag set by higher levels to

	 * control this. For now if the tables use sme_set then so do the ptes.

	 */

	if (pt_feature(common, PT_FEAT_X86_64_AMD_ENCRYPT_TABLES))

	if (pt_feature(common, PT_FEAT_X86_64_AMD_ENCRYPT_TABLES) &&

	    !(iommu_prot & IOMMU_MMIO))

		pte = __sme_set(pte);



	attrs->descriptor_bits = pte;