Commit e28e6b69 authored by Anup Patel's avatar Anup Patel Committed by Anup Patel
Browse files

RISC-V: KVM: Use nacl_csr_xyz() for accessing H-extension CSRs 



When running under some other hypervisor, prefer nacl_csr_xyz()
for accessing H-extension CSRs in the run-loop. This makes CSR
access faster whenever SBI nested acceleration is available.

Signed-off-by: default avatarAnup Patel <apatel@ventanamicro.com>
Reviewed-by: default avatarAtish Patra <atishp@rivosinc.com>
Link: https://lore.kernel.org/r/20241020194734.58686-10-apatel@ventanamicro.com


Signed-off-by: default avatarAnup Patel <anup@brainfault.org>
parent d466c19c

arch/riscv/kvm/mmu.c

+2 −2
Original line number Diff line number Diff line
@@ -15,7 +15,7 @@ 
#include <linux/vmalloc.h>

#include <linux/kvm_host.h>

#include <linux/sched/signal.h>

#include <asm/csr.h>

#include <asm/kvm_nacl.h>

#include <asm/page.h>

#include <asm/pgtable.h>
@@ -732,7 +732,7 @@ void kvm_riscv_gstage_update_hgatp(struct kvm_vcpu *vcpu) 
	hgatp |= (READ_ONCE(k->vmid.vmid) << HGATP_VMID_SHIFT) & HGATP_VMID;

	hgatp |= (k->pgd_phys >> PAGE_SHIFT) & HGATP_PPN;



	csr_write(CSR_HGATP, hgatp);

	ncsr_write(CSR_HGATP, hgatp);



	if (!kvm_riscv_gstage_vmid_bits())

		kvm_riscv_local_hfence_gvma_all();

arch/riscv/kvm/vcpu.c

+71 −32
Original line number Diff line number Diff line
@@ -17,8 +17,8 @@ 
#include <linux/sched/signal.h>

#include <linux/fs.h>

#include <linux/kvm_host.h>

#include <asm/csr.h>

#include <asm/cacheflush.h>

#include <asm/kvm_nacl.h>

#include <asm/kvm_vcpu_vector.h>



#define CREATE_TRACE_POINTS
@@ -368,10 +368,10 @@ void kvm_riscv_vcpu_sync_interrupts(struct kvm_vcpu *vcpu) 
	struct kvm_vcpu_csr *csr = &vcpu->arch.guest_csr;



	/* Read current HVIP and VSIE CSRs */

	csr->vsie = csr_read(CSR_VSIE);

	csr->vsie = ncsr_read(CSR_VSIE);



	/* Sync-up HVIP.VSSIP bit changes does by Guest */

	hvip = csr_read(CSR_HVIP);

	hvip = ncsr_read(CSR_HVIP);

	if ((csr->hvip ^ hvip) & (1UL << IRQ_VS_SOFT)) {

		if (hvip & (1UL << IRQ_VS_SOFT)) {

			if (!test_and_set_bit(IRQ_VS_SOFT,
@@ -568,9 +568,31 @@ static void kvm_riscv_vcpu_setup_config(struct kvm_vcpu *vcpu) 


void kvm_arch_vcpu_load(struct kvm_vcpu *vcpu, int cpu)

{

	void *nsh;

	struct kvm_vcpu_csr *csr = &vcpu->arch.guest_csr;

	struct kvm_vcpu_config *cfg = &vcpu->arch.cfg;



	if (kvm_riscv_nacl_sync_csr_available()) {

		nsh = nacl_shmem();

		nacl_csr_write(nsh, CSR_VSSTATUS, csr->vsstatus);

		nacl_csr_write(nsh, CSR_VSIE, csr->vsie);

		nacl_csr_write(nsh, CSR_VSTVEC, csr->vstvec);

		nacl_csr_write(nsh, CSR_VSSCRATCH, csr->vsscratch);

		nacl_csr_write(nsh, CSR_VSEPC, csr->vsepc);

		nacl_csr_write(nsh, CSR_VSCAUSE, csr->vscause);

		nacl_csr_write(nsh, CSR_VSTVAL, csr->vstval);

		nacl_csr_write(nsh, CSR_HEDELEG, cfg->hedeleg);

		nacl_csr_write(nsh, CSR_HVIP, csr->hvip);

		nacl_csr_write(nsh, CSR_VSATP, csr->vsatp);

		nacl_csr_write(nsh, CSR_HENVCFG, cfg->henvcfg);

		if (IS_ENABLED(CONFIG_32BIT))

			nacl_csr_write(nsh, CSR_HENVCFGH, cfg->henvcfg >> 32);

		if (riscv_has_extension_unlikely(RISCV_ISA_EXT_SMSTATEEN)) {

			nacl_csr_write(nsh, CSR_HSTATEEN0, cfg->hstateen0);

			if (IS_ENABLED(CONFIG_32BIT))

				nacl_csr_write(nsh, CSR_HSTATEEN0H, cfg->hstateen0 >> 32);

		}

	} else {

		csr_write(CSR_VSSTATUS, csr->vsstatus);

		csr_write(CSR_VSIE, csr->vsie);

		csr_write(CSR_VSTVEC, csr->vstvec);
@@ -589,6 +611,7 @@ void kvm_arch_vcpu_load(struct kvm_vcpu *vcpu, int cpu) 
			if (IS_ENABLED(CONFIG_32BIT))

				csr_write(CSR_HSTATEEN0H, cfg->hstateen0 >> 32);

		}

	}



	kvm_riscv_gstage_update_hgatp(vcpu);
@@ -610,6 +633,7 @@ void kvm_arch_vcpu_load(struct kvm_vcpu *vcpu, int cpu) 


void kvm_arch_vcpu_put(struct kvm_vcpu *vcpu)

{

	void *nsh;

	struct kvm_vcpu_csr *csr = &vcpu->arch.guest_csr;



	vcpu->cpu = -1;
@@ -625,6 +649,18 @@ void kvm_arch_vcpu_put(struct kvm_vcpu *vcpu) 
					 vcpu->arch.isa);

	kvm_riscv_vcpu_host_vector_restore(&vcpu->arch.host_context);



	if (kvm_riscv_nacl_available()) {

		nsh = nacl_shmem();

		csr->vsstatus = nacl_csr_read(nsh, CSR_VSSTATUS);

		csr->vsie = nacl_csr_read(nsh, CSR_VSIE);

		csr->vstvec = nacl_csr_read(nsh, CSR_VSTVEC);

		csr->vsscratch = nacl_csr_read(nsh, CSR_VSSCRATCH);

		csr->vsepc = nacl_csr_read(nsh, CSR_VSEPC);

		csr->vscause = nacl_csr_read(nsh, CSR_VSCAUSE);

		csr->vstval = nacl_csr_read(nsh, CSR_VSTVAL);

		csr->hvip = nacl_csr_read(nsh, CSR_HVIP);

		csr->vsatp = nacl_csr_read(nsh, CSR_VSATP);

	} else {

		csr->vsstatus = csr_read(CSR_VSSTATUS);

		csr->vsie = csr_read(CSR_VSIE);

		csr->vstvec = csr_read(CSR_VSTVEC);
@@ -635,6 +671,7 @@ void kvm_arch_vcpu_put(struct kvm_vcpu *vcpu) 
		csr->hvip = csr_read(CSR_HVIP);

		csr->vsatp = csr_read(CSR_VSATP);

	}

}



static void kvm_riscv_check_vcpu_requests(struct kvm_vcpu *vcpu)

{
@@ -688,7 +725,7 @@ static void kvm_riscv_update_hvip(struct kvm_vcpu *vcpu) 
{

	struct kvm_vcpu_csr *csr = &vcpu->arch.guest_csr;



	csr_write(CSR_HVIP, csr->hvip);

	ncsr_write(CSR_HVIP, csr->hvip);

	kvm_riscv_vcpu_aia_update_hvip(vcpu);

}
@@ -735,7 +772,9 @@ static void noinstr kvm_riscv_vcpu_enter_exit(struct kvm_vcpu *vcpu) 
	kvm_riscv_vcpu_swap_in_guest_state(vcpu);

	guest_state_enter_irqoff();



	hcntx->hstatus = csr_swap(CSR_HSTATUS, gcntx->hstatus);

	hcntx->hstatus = ncsr_swap(CSR_HSTATUS, gcntx->hstatus);



	nsync_csr(-1UL);



	__kvm_riscv_switch_to(&vcpu->arch);
@@ -870,8 +909,8 @@ int kvm_arch_vcpu_ioctl_run(struct kvm_vcpu *vcpu) 
		trap.sepc = vcpu->arch.guest_context.sepc;

		trap.scause = csr_read(CSR_SCAUSE);

		trap.stval = csr_read(CSR_STVAL);

		trap.htval = csr_read(CSR_HTVAL);

		trap.htinst = csr_read(CSR_HTINST);

		trap.htval = ncsr_read(CSR_HTVAL);

		trap.htinst = ncsr_read(CSR_HTINST);



		/* Syncup interrupts state with HW */

		kvm_riscv_vcpu_sync_interrupts(vcpu);

arch/riscv/kvm/vcpu_timer.c

+14 −14
Original line number Diff line number Diff line
@@ -11,8 +11,8 @@ 
#include <linux/kvm_host.h>

#include <linux/uaccess.h>

#include <clocksource/timer-riscv.h>

#include <asm/csr.h>

#include <asm/delay.h>

#include <asm/kvm_nacl.h>

#include <asm/kvm_vcpu_timer.h>



static u64 kvm_riscv_current_cycles(struct kvm_guest_timer *gt)
@@ -72,10 +72,10 @@ static int kvm_riscv_vcpu_timer_cancel(struct kvm_vcpu_timer *t) 
static int kvm_riscv_vcpu_update_vstimecmp(struct kvm_vcpu *vcpu, u64 ncycles)

{

#if defined(CONFIG_32BIT)

		csr_write(CSR_VSTIMECMP, ncycles & 0xFFFFFFFF);

		csr_write(CSR_VSTIMECMPH, ncycles >> 32);

	ncsr_write(CSR_VSTIMECMP, ncycles & 0xFFFFFFFF);

	ncsr_write(CSR_VSTIMECMPH, ncycles >> 32);

#else

		csr_write(CSR_VSTIMECMP, ncycles);

	ncsr_write(CSR_VSTIMECMP, ncycles);

#endif

	return 0;

}
@@ -289,10 +289,10 @@ static void kvm_riscv_vcpu_update_timedelta(struct kvm_vcpu *vcpu) 
	struct kvm_guest_timer *gt = &vcpu->kvm->arch.timer;



#if defined(CONFIG_32BIT)

	csr_write(CSR_HTIMEDELTA, (u32)(gt->time_delta));

	csr_write(CSR_HTIMEDELTAH, (u32)(gt->time_delta >> 32));

	ncsr_write(CSR_HTIMEDELTA, (u32)(gt->time_delta));

	ncsr_write(CSR_HTIMEDELTAH, (u32)(gt->time_delta >> 32));

#else

	csr_write(CSR_HTIMEDELTA, gt->time_delta);

	ncsr_write(CSR_HTIMEDELTA, gt->time_delta);

#endif

}
@@ -306,10 +306,10 @@ void kvm_riscv_vcpu_timer_restore(struct kvm_vcpu *vcpu) 
		return;



#if defined(CONFIG_32BIT)

	csr_write(CSR_VSTIMECMP, (u32)t->next_cycles);

	csr_write(CSR_VSTIMECMPH, (u32)(t->next_cycles >> 32));

	ncsr_write(CSR_VSTIMECMP, (u32)t->next_cycles);

	ncsr_write(CSR_VSTIMECMPH, (u32)(t->next_cycles >> 32));

#else

	csr_write(CSR_VSTIMECMP, t->next_cycles);

	ncsr_write(CSR_VSTIMECMP, t->next_cycles);

#endif



	/* timer should be enabled for the remaining operations */
@@ -327,10 +327,10 @@ void kvm_riscv_vcpu_timer_sync(struct kvm_vcpu *vcpu) 
		return;



#if defined(CONFIG_32BIT)

	t->next_cycles = csr_read(CSR_VSTIMECMP);

	t->next_cycles |= (u64)csr_read(CSR_VSTIMECMPH) << 32;

	t->next_cycles = ncsr_read(CSR_VSTIMECMP);

	t->next_cycles |= (u64)ncsr_read(CSR_VSTIMECMPH) << 32;

#else

	t->next_cycles = csr_read(CSR_VSTIMECMP);

	t->next_cycles = ncsr_read(CSR_VSTIMECMP);

#endif

}