Commit e2944dc6 authored by Lad Prabhakar's avatar Lad Prabhakar Committed by Biju Das
Browse files

drm: renesas: rz-du: mipi_dsi: Add function pointers for configuring VCLK and mode validation 



Introduce `dphy_conf_clks` and `dphy_mode_clk_check` callbacks in
`rzg2l_mipi_dsi_hw_info` to configure the VCLK and validate
supported display modes.

On the RZ/V2H(P) SoC, the DSI PLL dividers need to be as accurate as
possible. To ensure compatibility with both RZ/G2L and RZ/V2H(P) SoCs,
function pointers are introduced.

Modify `rzg2l_mipi_dsi_startup()` to use `dphy_conf_clks` for clock
configuration and `rzg2l_mipi_dsi_bridge_mode_valid()` to invoke
`dphy_mode_clk_check` for mode validation.

This change ensures proper operation across different SoC variants
by allowing fine-grained control over clock configuration and mode
validation.

Co-developed-by: default avatarFabrizio Castro <fabrizio.castro.jz@renesas.com>
Signed-off-by: default avatarFabrizio Castro <fabrizio.castro.jz@renesas.com>
Signed-off-by: default avatarLad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: default avatarBiju Das <biju.das.jz@bp.renesas.com>
Signed-off-by: default avatarBiju Das <biju.das.jz@bp.renesas.com>
Link: https://lore.kernel.org/r/20250609225630.502888-10-prabhakar.mahadev-lad.rj@bp.renesas.com
parent 7c1e102c

drivers/gpu/drm/renesas/rz-du/rzg2l_mipi_dsi.c

+45 −20
Original line number Diff line number Diff line
@@ -42,6 +42,10 @@ struct rzg2l_mipi_dsi_hw_info { 
	int (*dphy_init)(struct rzg2l_mipi_dsi *dsi, u64 hsfreq_millihz);

	void (*dphy_startup_late_init)(struct rzg2l_mipi_dsi *dsi);

	void (*dphy_exit)(struct rzg2l_mipi_dsi *dsi);

	int (*dphy_conf_clks)(struct rzg2l_mipi_dsi *dsi, unsigned long mode_freq,

			      u64 *hsfreq_millihz);

	unsigned int (*dphy_mode_clk_check)(struct rzg2l_mipi_dsi *dsi,

					    unsigned long mode_freq);

	u32 phy_reg_offset;

	u32 link_reg_offset;

	unsigned long min_dclk;
@@ -285,12 +289,39 @@ static void rzg2l_mipi_dsi_dphy_exit(struct rzg2l_mipi_dsi *dsi) 
	reset_control_assert(dsi->rstc);

}



static int rzg2l_dphy_conf_clks(struct rzg2l_mipi_dsi *dsi, unsigned long mode_freq,

				u64 *hsfreq_millihz)

{

	unsigned long vclk_rate;

	unsigned int bpp;



	clk_set_rate(dsi->vclk, mode_freq * KILO);

	vclk_rate = clk_get_rate(dsi->vclk);

	if (vclk_rate != mode_freq * KILO)

		dev_dbg(dsi->dev, "Requested vclk rate %lu, actual %lu mismatch\n",

			mode_freq * KILO, vclk_rate);

	/*

	 * Relationship between hsclk and vclk must follow

	 * vclk * bpp = hsclk * 8 * lanes

	 * where vclk: video clock (Hz)

	 *       bpp: video pixel bit depth

	 *       hsclk: DSI HS Byte clock frequency (Hz)

	 *       lanes: number of data lanes

	 *

	 * hsclk(bit) = hsclk(byte) * 8 = hsfreq

	 */

	bpp = mipi_dsi_pixel_format_to_bpp(dsi->format);

	*hsfreq_millihz = DIV_ROUND_CLOSEST_ULL(mul_u32_u32(vclk_rate, bpp * MILLI),

						dsi->lanes);



	return 0;

}



static int rzg2l_mipi_dsi_startup(struct rzg2l_mipi_dsi *dsi,

				  const struct drm_display_mode *mode)

{

	unsigned long hsfreq, vclk_rate;

	unsigned long hsfreq;

	u64 hsfreq_millihz;

	unsigned int bpp;

	u32 txsetr;

	u32 clstptsetr;

	u32 lptrnstsetr;
@@ -305,24 +336,9 @@ static int rzg2l_mipi_dsi_startup(struct rzg2l_mipi_dsi *dsi, 
	if (ret < 0)

		return ret;



	clk_set_rate(dsi->vclk, mode->clock * KILO);

	vclk_rate = clk_get_rate(dsi->vclk);

	if (vclk_rate != mode->clock * KILO)

		dev_dbg(dsi->dev, "Requested vclk rate %lu, actual %lu mismatch\n",

			mode->clock * KILO, vclk_rate);



	/*

	 * Relationship between hsclk and vclk must follow

	 * vclk * bpp = hsclk * 8 * lanes

	 * where vclk: video clock (Hz)

	 *       bpp: video pixel bit depth

	 *       hsclk: DSI HS Byte clock frequency (Hz)

	 *       lanes: number of data lanes

	 *

	 * hsclk(bit) = hsclk(byte) * 8 = hsfreq

	 */

	bpp = mipi_dsi_pixel_format_to_bpp(dsi->format);

	hsfreq_millihz = DIV_ROUND_CLOSEST_ULL(mul_u32_u32(vclk_rate, bpp * MILLI), dsi->lanes);

	ret = dsi->info->dphy_conf_clks(dsi, mode->clock, &hsfreq_millihz);

	if (ret < 0)

		goto err_phy;



	ret = dsi->info->dphy_init(dsi, hsfreq_millihz);

	if (ret < 0)
@@ -646,6 +662,14 @@ rzg2l_mipi_dsi_bridge_mode_valid(struct drm_bridge *bridge, 
	if (mode->clock < dsi->info->min_dclk)

		return MODE_CLOCK_LOW;



	if (dsi->info->dphy_mode_clk_check) {

		enum drm_mode_status status;



		status = dsi->info->dphy_mode_clk_check(dsi, mode->clock);

		if (status != MODE_OK)

			return status;

	}



	return MODE_OK;

}
@@ -1030,6 +1054,7 @@ static void rzg2l_mipi_dsi_remove(struct platform_device *pdev) 
static const struct rzg2l_mipi_dsi_hw_info rzg2l_mipi_dsi_info = {

	.dphy_init = rzg2l_mipi_dsi_dphy_init,

	.dphy_exit = rzg2l_mipi_dsi_dphy_exit,

	.dphy_conf_clks = rzg2l_dphy_conf_clks,

	.link_reg_offset = 0x10000,

	.min_dclk = 5803,

	.max_dclk = 148500,